ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 141

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.3.4
17.3.5
17.3.6
8235B–AVR–04/11
Address Packet
Data Packet
Transaction
After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is
always transmitted by the Master. A slave recognizing its address will ACK the address by pull-
ing the data line low the next SCL cycle, while all other slaves should keep the TWI lines
released, and wait for the next START and address. The 7-bit address, the R/W bit and the
acknowledge bit combined is the address packet. Only one address packet for each START
condition is given, also when 10-bit addressing is used.
The R/W specifies the direction of the transaction. If the R/W bit is low, it indicates a Master
Write transaction, and the master will transmit its data after the slave has acknowledged its
address. Opposite, for a Master Read operation the slave will start to transmit data after
acknowledging its address.
Data packets succeed an address packet or another data packet. All data packets are nine bits
long, consisting of one data byte and an acknowledge bit. The direction bit in the previous
address packet determines the direction in which the data is transferred.
A transaction is the complete transfer from a START to a STOP condition, including any
Repeated START conditions in between. The TWI standard defines three fundamental transac-
tion modes: Master Write, Master Read, and combined transaction.
Figure 17-5
ing a START condition (S) followed by an address packet with direction bit set to zero
(ADDRESS+W).
Figure 17-5. Master Write Transaction
Given that the slave acknowledges the address, the master can start transmitting data (DATA)
and the slave will ACK or NACK (A/A) each byte. If no data packets are to be transmitted, the
master terminates the transaction by issuing a STOP condition (P) directly after the address
packet. There are no limitations to the number of data packets that can be transferred. If the
slave signal a NACK to the data, the master must assume that the slave cannot receive any
more data and terminate the transaction.
Figure 17-6
ing a START condition followed by an address packet with direction bit set to one (ADRESS+R).
The addressed slave must acknowledge the address for the master to be allowed to continue
the transaction.
illustrates the Master Write transaction. The master initiates the transaction by issu-
illustrates the Master Read transaction. The master initiates the transaction by issu-
ATtiny20
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