ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 35

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8.4.2
8.5
8.5.1
8235B–AVR–04/11
Register Description
Code Examples
WDTCSR – Watchdog Timer Control and Status Register
The following code example shows how to turn off the WDT. The example assumes that inter-
rupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during
execution of these functions.
Note:
• Bit 7 – WDIF: Watchdog Timer Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the WDIE
is set, the Watchdog Time-out Interrupt is requested.
• Bit 6 – WDIE: Watchdog Timer Interrupt Enable
When this bit is written to one, the Watchdog interrupt request is enabled. If WDE is cleared in
combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding
interrupt is requested if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Bit
0x31
Read/Write
Initial Value
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in
andi
out
; Write signature for change enable of protected I/O register
ldi r16, 0xD8
out CCP, r16
; Within four instruction cycles, turn off WDT
ldi r16, (0<<WDE)
out WDTCSR, r16
ret
See
“Code Examples” on page
r16, RSTFLR
RSTFLR, r16
WDIF
r16, ~(1<<WDRF)
R/W
7
0
WDIE
R/W
6
0
WDP3
R/W
5
0
6.
R
4
–
0
WDE
R/W
X
3
WDP2
R/W
2
0
WDP1
R/W
1
0
WDP0
R/W
0
0
ATtiny20
WDTCSR
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