ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 140

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.3.1
17.3.2
17.3.3
140
ATtiny20
Electrical Characteristics
START and STOP Conditions
Bit Transfer
The master provides the clock signal for the transaction, but a device connected to the bus is
allowed to stretch the low level period of the clock to decrease the clock speed.
The TWI follows the electrical specifications and timing of I
with SMBus” on page
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a
transaction. The master issues a START condition(S) by indicating a high to low transition on the
SDA line while the SCL line is kept high. The master completes the transaction by issuing a
STOP condition (P), indicated by a low to high transition on the SDA line while SCL line is kept
high.
Figure 17-3. START and STOP Conditions
Multiple START conditions can be issued during a single transaction. A START condition not
directly following a STOP condition, are named a Repeated START condition (Sr).
As illustrated by
period of the SCL line. Consequently the SDA value can only be changed during the low period
of the clock. This is ensured in hardware by the TWI module.
Figure 17-4. Data Validity
Combining bit transfers results in the formation of address and data packets. These packets
consist of 8 data bits (one byte) with the most significant bit transferred first, plus a single bit not-
acknowledge (NACK) or acknowledge (ACK) response. The addressed device signals ACK by
pulling the SCL line low, and NACK by leaving the line SCL high during the ninth clock cycle.
Figure 17-4
144.
a bit transferred on the SDA line must be stable for the entire high
2
C and SMBus. See
“Compatibility
8235B–AVR–04/11