ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 113

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.3
8235B–AVR–04/11
Operation
Figure 15-1. Analog to Digital Converter Block Schematic
In order to be able to use the ADC the Power Reduction bit, PRADC, in the Power Reduction
Register must be disabled. This is done by clearing the PRADC bit. See
tion Register” on page 29
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
ADC7
ADC7
ADC6
ADC6
ADC5
ADC5
ADC4
ADC4
ADC3
ADC3
ADC2
ADC2
ADC1
ADC1
ADC0
ADC0
V
CC
CC
TEMPERATURE
TEMPERATURE
REFERENCE
REFERENCE
INTERNAL
INTERNAL
SENSOR
SENSOR
8-BIT DATA BUS
AGND
ADMUX
ADMUX
DECODER
DECODER
for more details.
ADCSRB
ADCSRB
INPUT
INPUT
MUX
MUX
TRIGGER
TRIGGER
SELECT
SELECT
10-BIT DAC
10-BIT DAC
PRESCALER
PRESCALER
ADCSRA
ADCSRA
CONVERSION LOGIC
CONVERSION LOGIC
“PRR – Power Reduc-
SAMPLE & HOLD
SAMPLE & HOLD
COMPARATOR
COMPARATOR
-
+
ATtiny20
ADCH+ADCL
ADCH+ADCL
ADC MUX OUTPUT
ADC MUX OUTPUT
ADC IRQ
ADC IRQ
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