ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 160

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.5.8
18.6
18.7
160
Accessing the Non-Volatile Memory Controller
Control and Status Space Register Descriptions
ATtiny20
SKEY - Serial KEY signaling
The SKEY instruction is used to signal the activation key that enables NVM programming. The
SKEY instruction is followed by the 8 data bytes that includes the activation key, as shown in
Table
Table 18-9.
By default, NVM programming is not enabled. In order to access the NVM Controller and be able
to program the non-volatile memories, a unique key must be sent using the SKEY instruction.
The 64-bit key that will enable NVM programming is given in
Table 18-10. Enable Key for Non-Volatile Memory Programming
After the key has been given, the Non-Volatile Memory Enable (NVMEN) bit in the TPI Status
Register (TPISR) must be polled until the Non-Volatile memory has been enabled.
NVM programming is disabled by writing a logical zero to the NVMEN bit in TPISR.
The control and status registers of the Tiny Programming Interface are mapped in the Control
and Status Space (CSS) of the interface. These registers are not part of the I/O register map
and are accessible via SLDCS and SSTCS instructions, only. The control and status registers
are directly involved in configuration and status monitoring of the TPI.
A summary of CSS registers is shown in
Table 18-11. Summary of Control and Status Registers
Operation
Key
Key
NVM Program Enable
Addr.
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
←
18-9.
{8[data}}
Name
TPIIR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
The Serial KEY signaling (SKEY) Instruction
Bit 7
–
–
–
–
–
–
–
–
–
–
–
–
Opcode
1110 0000
Bit 6
–
–
–
–
–
–
–
–
–
–
–
–
Tiny Programming Interface Identification Code
Table
Bit 5
–
–
–
–
–
–
–
–
–
–
–
–
18-11.
Remarks
Data bytes follow after instruction
Value
0x1289AB45CDD888FF
Bit 4
–
–
–
–
–
–
–
–
–
–
–
–
Bit 3
Table
–
–
–
–
–
–
–
–
–
–
–
–
18-10.
Bit 2
–
–
–
–
–
–
–
–
–
–
–
–
Bit 1
–
–
–
–
–
–
–
–
–
–
–
–
8235B–AVR–04/11
Bit 0
–
–
–
–
–
–
–
–
–
–
–
–