ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 13

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.8
4.8.1
4.8.2
8235B–AVR–04/11
Register Description
CCP – Configuration Change Protection Register
SPH and SPL — Stack Pointer Registers
• Bits 7:0 – CCP[7:0]: Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written
with the correct signature. After CCP is written the protected I/O registers may be written to dur-
ing the next four CPU instruction cycles. All interrupts are ignored during these cycles. After
these cycles interrupts are automatically handled again by the CPU, and any pending interrupts
will be executed according to their priority.
When the protected I/O register signature is written, CCP0 will read as one as long as the pro-
tected feature is enabled, while CCP[7:1] will always read as zero.
Table 4-1
Table 4-1.
Notes:
• Bits 7:0 – SP[7:0]: Stack Pointer
The Stack Pointer register points to the top of the stack, which is implemented growing from
higher memory locations to lower memory locations. Hence, a stack PUSH command decreases
the stack pointer.
The stack space in the data SRAM must be defined by the program before any subroutine calls
are executed or interrupts are enabled.
In ATtiny20, the SPH register has not been implemented.
Bit
0x3C
Read/Write
Initial Value
Initial Value
Read/Write
Bit
0x3E
0x3D
Bit
Read/Write
Initial Value
Signature
0xD8
1. Only WDE and WDP[3:0] bits are protected in WDTCSR.
2. Only BODS bit is protected in MCUCR.
shows the signatures that are in recognised.
Signatures Recognised by the Configuration Change Protection Register
RAMEND
SP7
R/W
Group
IOREG: CLKMSR, CLKPSR, WDTCSR
W
7
0
15
R
0
–
7
RAMEND
SP6
R/W
W
6
0
14
R
0
–
6
RAMEND
SP5
R/W
W
5
0
13
R
0
–
5
RAMEND
SP4
R/W
W
4
0
12
R
0
–
4
CCP[7:0]
RAMEND
(1)
SP3
R/W
W
3
0
11
, MCUCR
R
–
3
0
RAMEND
SP2
R/W
W
(2)
2
0
10
R
2
0
–
Description
Protected I/O register
RAMEND
SP1
R/W
W
1
0
R
9
1
0
–
ATtiny20
RAMEND
R/W
R/W
SP0
0
0
R
8
0
0
–
CCP
SPH
SPL
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