ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 147

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.2
8235B–AVR–04/11
TWSCRB – TWI Slave Control Register B
• Bit 4 – TWASIE: TWI Address/Stop Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the
address/stop interrupt flag (TWASIF) in TWSSRA is set.
• Bit 3 – TWEN: Two-Wire Interface Enable
When this bit is set the slave Two-Wire Interface is enabled.
• Bit 2 – TWSIE: TWI Stop Interrupt Enable
Setting the Stop Interrupt Enable (TWSIE) bit will set the TWASIF in the TWSSRA register when
a STOP condition is detected.
• Bit 1 – TWPME: TWI Promiscuous Mode Enable
When this bit is set the address match logic of the slave TWI responds to all received addresses.
When this bit is cleared the address match logic uses the TWSA register to determine which
address to recognize as its own.
• Bit 0 – TWSME: TWI Smart Mode Enable
When this bit is set the TWI slave enters Smart Mode, where the Acknowledge Action is sent
immediately after the TWI data register (TWSD) has been read. Acknowledge Action is defined
by the TWAA bit in TWSCRB.
When this bit is cleared the Acknowledge Action is sent after TWCMDn bits in TWSCRB are
written to 1X.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 2 – TWAA: TWI Acknowledge Action
This bit defines the slave's acknowledge behavior after an address or data byte has been
received from the master. Depending on the TWSME bit in TWSCRA the Acknowledge Action is
executed either when a valid command has been written to TWCMDn bits, or when the data reg-
ister has been read. Acknowledge action is also executed if clearing TWAIF flag after address
match or TWDIF flag during master transmit. See
Table 17-1.
Bit
0x2C
Read/Write
Initial Value
TWAA
0
1
Acknowledge Action of TWI Slave
R
7
–
0
Action
Send ACK
Send NACK
R
6
–
0
R
5
–
0
TWSME
0
1
0
1
R
4
–
0
Table 17-1
When
When TWCMDn bits are written to 10 or 11
When TWSD is read
When TWCMDn bits are written to 10 or 11
When TWSD is read
R
3
–
0
TWAA
for details.
R/W
2
0
TWCMD1
W
1
0
TWCMD0
ATtiny20
W
0
0
TWSCRB
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