ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 39

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.2
8235B–AVR–04/11
External Interrupts
A typical and general setup for interrupt vector addresses in ATtiny20 is shown in the program
example below.
Note:
External Interrupts are triggered by the INT0 pin or any of the PCINT[11:0] pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as out-
puts. This feature provides a way of generating a software interrupt.
Pin change 0 interrupts PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1
interrupts PCI1 will trigger if any enabled PCINT[11:8] pin toggles. The PCMSK0 and PCMSK1
Registers control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT[11:0] are detected asynchronously, which means that these interrupts can be used for
waking the part also from sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as
shown in
and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note
that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock,
as described in
Assembly Code Example
.org 0x0000
RESET:
rjmp RESET
rjmp INT0_ISR
rjmp PCINT0_ISR
rjmp PCINT1_ISR
rjmp WDT_ISR
rjmp TIM1_CAPT_ISR
rjmp TIM1_COMPA_ISR
rjmp TIM1_COMPB_ISR
rjmp TIM1_OVF_ISR
rjmp TIM0_COMPA_ISR
rjmp TIM0_COMPB_ISR
rjmp TIM0_OVF_ISR
rjmp ANA_COMP_ISR
rjmp ADC_ISR
rjmp TWI_SLAVE_ISR
rjmp SPI_ISR
rjmp QTRIP_ISR
<instr>
...
See
“MCUCR – MCU Control Register” on page
“Code Examples” on page
“Clock System” on page
6.
18.
;Set address of next statement
; Address 0x0000
; Address 0x0001
; Address 0x0002
; Address 0x0003
; Address 0x0004
; Address 0x0005
; Address 0x0006
; Address 0x0007
; Address 0x0008
; Address 0x0009
; Address 0x000A
; Address 0x000B
; Address 0x000C
; Address 0x000D
; Address 0x000E
; Address 0x000F
; Address 0x0010
; Main program start
; Address 0x0011
41. When the INT0 interrupt is enabled
ATtiny20
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