ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 150

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.4
17.5.5
150
ATtiny20
TWSA – TWI Slave Address Register
TWSD – TWI Slave Data Register
• Bit 2 – TWBE: TWI Bus Error
This bit is set when an illegal bus condition has occured during a transfer. An illegal bus condi-
tion occurs if a Repeated START or STOP condition is detected, and the number of bits from the
previous START condition is not a multiple of nine.
This bit is cleared by writing a one to it.
For bus errors to be detected, the system clock frequency must be at least four times the SCL
frequency.
• Bit 1 – TWDIR: TWI Read/Write Direction
This bit indicates the direction bit from the last address packet received from a master. When
this bit is one, a master read operation is in progress. When the bit is zero a master write opera-
tion is in progress.
• Bit 0 – TWAS: TWI Address or Stop
This bit indicates why the TWASIF bit was last set. If zero, a stop condition caused TWASIF to
be set. If one, address detection caused TWASIF to be set.
The slave address register contains the TWI slave address used by the slave address match
logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address rec-
ognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave
address. The least significant bit (TWSA0) is used for general call address recognition. Setting
TWSA0 enables general call address recognition logic.
When using 10-bit addressing the address match logic only support hardware address recogni-
tion of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent
bits 9 and 8 of the slave address. The next byte received is then bits 7 to 0 in the 10-bit address,
but this must be handled by software.
When the address match logic detects that a valid address byte has been received, the TWASIF
is set and the TWDIR flag is updated.
If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on
the TWI bus. TWSA is not used in this mode.
The data register is used when transmitting and received data. During transfer, data is shifted
from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed
during byte transfers. This is protected in hardware. The data register can only be accessed
when the SCL line is held low by the slave, i.e. when TWCH is set.
Bit
0x2A
Read/Write
Initial Value
Bit
0x28
Read/Write
Initial Value
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
TWSA[7:0]
TWSD[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
8235B–AVR–04/11
TWSA
TWSD