ATtiny20 Atmel Corporation, ATtiny20 Datasheet - Page 103

• Manufacturer Part Number: ATtiny20
• Manufacturer: Atmel Corporation

Specifications of ATtiny20

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 5
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.11.5
12.11.6
12.11.7
12.11.8
8235B–AVR–04/11
OCR1AH and OCR1AL – Output Compare Register 1 A
OCR1BH and OCR1BL – Output Compare Register 1 B
ICR1H and ICR1L – Input Capture Register 1
TIMSK – Timer/Counter Interrupt Mask Register
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See “Interrupts” on page 66.) is executed when the ICF1 Flag, located in TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Bit
0x1F
0x1E
Read/Write
Initial Value
Bit
0x1D
0x1C
Read/Write
Initial Value
Bit
0x1B
0x1A
Read/Write
Initial Value
Bit
0x26
Read/Write
Initial Value
“Accessing 16-bit Registers” on page
ICIE1
R/W
R/W
R/W
R/W
7
0
7
0
“Accessing 16-bit Registers” on page
7
0
7
0
R/W
R/W
R/W
R
6
0
6
0
6
0
6
–
0
OCIE1B
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
OCIE1A
R/W
R/W
R/W
R/W
4
OCR1A[15:8]
0
4
OCR1B[15:8]
0
4
0
OCR1A[7:0]
OCR1B[7:0]
4
0
ICR1[15:8]
ICR1[7:0]
95.
TOIE1
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
95.
OCIE0B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE0A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
ATtiny20
R/W
R/W
R/W
TOIE0
R/W
0
0
0
0
0
0
0
0
OCR1AH
OCR1AL
OCR1BH
OCR1BL
ICR1H
ICR1L
TIMSK
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