XC2S50 Xilinx, Inc., XC2S50 Datasheet
XC2S50
Available stocks
Related parts for XC2S50
XC2S50 Summary of contents
Page 1
... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...
Page 2
... Unlimited reprogrammability - Very low cost Table 1: Spartan-II FPGA Family Members Logic System Gates Device Cells (Logic and RAM) XC2S15 432 XC2S30 972 XC2S50 1,728 XC2S100 2,700 100,000 XC2S150 3,888 150,000 XC2S200 5,292 200,000 Notes: 1. All user I/O counts do not include the four global clock/user input pins. See details in © ...
Page 3
Spartan-II 2.5V FPGA Family: Introduction and Ordering Information General Overview The Spartan-II family of FPGAs have a regular, flexible, pro- grammable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked ...
Page 4
... Industrial Table 3: Spartan-II User I/O Chart Maximum Device User I/O VQ100 XC2S15 86 XC2S30 132 XC2S50 176 XC2S100 196 XC2S150 260 XC2S200 284 Notes: 1. All user I/O counts do not include the four global clock/user input pins. DS001-1 (v2.4) September 3, 2003 Product Specification Spartan-II 2 ...
Page 5
... Updated Product Availability chart. Minor text edits. 09/03/03 2.4 Added device part marking. 4 XC2S50 -6 PQ 208 C Number of Pins / Package Type VQ100 100-pin Plastic Very Thin QFP CS144 144-ball Chip-Scale BGA TQ144 144-pin Plastic Thin QFP PQ208 208-pin Plastic QFP FG256 256-ball Fine Pitch BGA ...
Page 6
R The Spartan-II Family Data Sheet DS001-1, Spartan-II 2.5V FPGA Family: Introduction and Ordering Information (Module 1) DS001-2, Spartan-II 2.5V FPGA Family: DS001-3, Spartan-II 2.5V FPGA Family: DS001-4, Spartan-II 2.5V FPGA Family: DS001-1 (v2.4) September 3, 2003 Product Specification Spartan-II ...
Page 7
Spartan-II 2.5V FPGA Family: Introduction and Ordering Information 6 www.xilinx.com 1-800-255-7778 R DS001-1 (v2.4) September 3, 2003 Product Specification ...
Page 8
... OFF IFF © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS001-2 (v2.2) September 3, 2003 ...
Page 9
Spartan-II 2.5V FPGA Family: Functional Description In addition to the CLK and CE control signals, the three reg- isters share a Set/Reset (SR). For each register, this signal can be independently configured as a synchronous Set, a synchronous Reset, an ...
Page 10
R I/O Banking Some of the I/O standards described above require V and/or V voltages. These voltages are externally con- REF nected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can ...
Page 11
Spartan-II 2.5V FPGA Family: Functional Description Figure 3: Spartan-II CLB Slice (two identical slices in each CLB) In addition to Clock and Clock Enable signals, each slice has synchronous set and reset signals (SR and BY). SR forces a storage ...
Page 12
... Spartan-II device eight CLBs high will contain two memory blocks per column, and a total of four blocks. Table 4: Spartan-II Block RAM Amounts Spartan-II Device # of Blocks XC2S15 4 XC2S30 6 XC2S50 8 XC2S100 10 XC2S150 12 XC2S200 14 Each block RAM cell, as illustrated in chronous dual-ported 4096-bit RAM with independent con- trol signals for each port ...
Page 13
Spartan-II 2.5V FPGA Family: Functional Description them together with minimal routing delay • Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating the delay of the GRM To Adjacent GRM To To Adjacent Adjacent GRM GRM GRM To ...
Page 14
R Global Routing Global Routing resources distribute clocks and other sig- nals with very high fanout throughout the device. Spartan-II devices include two tiers of global routing resources referred to as primary and secondary global routing resources. • The primary ...
Page 15
Spartan-II 2.5V FPGA Family: Functional Description Table 6: Boundary-Scan Instructions Boundary-Scan Binary Command Code[4:0] EXTEST 00000 Enables boundary-scan SAMPLE 00001 Enables boundary-scan USR1 00010 USR2 00011 CFG_OUT 00100 CFG_IN 00101 INTEST 00111 Enables boundary-scan USRCODE 01000 IDCODE 01001 Enables shifting ...
Page 16
R IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB Bypass Register Instruction Register TDI Bit Sequence The bit sequence within each IOB is: In, Out, 3-State. The input-only pins contribute only the In bit to the boundary ...
Page 17
... Alliance CAE tools. The basic methodology for Spar- tan-II design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation (for example, Synopsys FPGA Express), while Xilinx provides proprietary architecture-specific tools for implementation. ...
Page 18
... For more information on configu- ration without a PROM, refer to XAPP098, The Low-Cost, Efficient Serial Configuration of Spartan FPGAs. Table 7: Spartan-II Configuration File Size Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Modes Spartan-II devices support the following four configuration modes: • ...
Page 19
Spartan-II 2.5V FPGA Family: Functional Description Signals There are two kinds of pins that are used to configure Spartan-II devices: Dedicated pins perform only specific configuration-related functions; the other pins can serve as general purpose I/Os once user operation has ...
Page 20
R ( PROGRAM INIT . Symbol T Power-on reset POR T Program latency PL T CCLK output delay (Master Serial ICCK mode only) T Program pulse width PROGRAM Notes: (referring to waveform above:) 1. Before configuration can begin, ...
Page 21
Spartan-II 2.5V FPGA Family: Functional Description By default, these operations are synchronized to CCLK. The entire start-up sequence lasts eight cycles, called C0-C7, after which the loaded design is fully functional. The default timing for start-up is shown in the ...
Page 22
R 3. DOUT Spartan-II (Master Serial) CCLK PROGRAM DONE GND PROGRAM Notes: If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 3.3K Ω resistor. 1. Figure ...
Page 23
Spartan-II 2.5V FPGA Family: Functional Description Master Serial Mode In Master Serial mode, the CCLK output of the FPGA drives a Xilinx PROM which feeds a serial stream of configuration data to the FPGA’s DIN input. Figure 14 Serial FPGA ...
Page 24
R DATA[7:0] CCLK WRITE BUSY CS(0) 330Ω DONE INIT PROGRAM Figure 17: Slave Parallel Configuration Circuit Diagram Multiple Spartan-II FPGAs can be configured using the Slave Parallel mode, and be made to start-up simulta- neously. To configure multiple devices in ...
Page 25
Spartan-II 2.5V FPGA Family: Functional Description If CCLK is slower than F , the FPGA will never assert CCNH BUSY. In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle. ...
Page 26
R CCLK CS WRITE T SMCCW T SMDCC DATA[7:0] T SMCKBY BUSY No Write Symbol T SMDCC T SMCCD T SMCSCC T SMCCCS T CCLK SMCCW T SMWCC T SMCKBY CCNH CCLK CS WRITE DATA[7:0] BUSY DS001-2 ...
Page 27
Spartan-II 2.5V FPGA Family: Functional Description Design Considerations This section contains more detailed design information on the following features: • Delay-Locked Loop . . . see page 20 • Block RAM . . . see page 24 • Versatile I/O ...
Page 28
R BUFGDLL Pin Descriptions Use the BUFGDLL macro as the simplest way to provide zero propagation delay for a high-fanout on-chip clock from an external input. This macro uses the IBUFG, CLKDLL and BUFG primitives to implement the most basic ...
Page 29
Spartan-II 2.5V FPGA Family: Functional Description CLKDLL primitive provides three phase-shifted versions of the CLK0 signal while CLKDLLHF provides only the 180 phase-shifted version. The relationship between phase shift and the corresponding period shift appears in The timing diagrams in ...
Page 30
R The LOC property uses the following form. LOC = DLL2 GCLKPAD3 DLL3 GCLKBUF3 GCLKPAD1 DLL1 GCLKBUF1 Figure 26: Orientation of DLLs Design Factors Use the following design considerations to avoid pitfalls and improve success designing with Xilinx devices. Input ...
Page 31
Spartan-II 2.5V FPGA Family: Functional Description could alternatively be implemented using similar connec- tions. IBUFG CLKDLL CLKIN CLK0 CLK90 CLKFB CLK180 CLK270 CLK2X IBUF CLKDV RST LOCKED Figure 28: DLL Deskew of Clock and 2x Multiple Because any single DLL ...
Page 32
write operation requires only one clock edge read operation requires only one clock edge. The output ports are latched with a self timed circuit to guar- antee a glitch free read. The state of the ...
Page 33
Spartan-II 2.5V FPGA Family: Functional Description Port Signals Each block RAM port operates independently of the others while accessing the same set of 4096 memory cells. Table 11 describes the depth and width aspect ratios for the block RAM memory. ...
Page 34
R The LOC properties use the following form: LOC = RAMB4_R#C# RAMB4_R0C0 is the upper left RAMB4 location on the device. Conflict Resolution The block RAM memory is a true dual-read/write port RAM that allows simultaneous access of the same ...
Page 35
Spartan-II 2.5V FPGA Family: Functional Description CLK ADDR DIN DOUT EN RST WE DISABLED Figure 32: Timing Diagram for Single-Port Block RAM Memory CLK_A ADDR_A 00 EN_A T BCCS WE_A DI_A AAAA DO_A CLK_B ADDR_B 00 EN_B WE_B DI_B 1111 ...
Page 36
R At the third rising edge of CLKA, the T violated with two writes to memory location 0x0F. The DOA and DOB busses reflect the contents of the DIA and DIB busses, but the stored value at 0x7E is invalid. ...
Page 37
Spartan-II 2.5V FPGA Family: Functional Description mance previously available only with ASICs and custom ICs. Each Versatile I/O block can support I/O standards. Supporting such a variety of I/O standards allows the sup- port of a wide ...
Page 38
R PCI — Peripheral Component Interface The Peripheral Component Interface (PCI) standard speci- fies support for both 33 MHz and 66 MHz PCI bus applica- tions. It uses a LVTTL input buffer and a push-pull output buffer. This standard does ...
Page 39
Spartan-II 2.5V FPGA Family: Functional Description bank with an HSTL standard (V CCO not 5V tolerant. The voltage reference signal is "banked" within the Spartan-II device on a half-edge basis such that for all pack- ages there are eight independent ...
Page 40
R OBUF An OBUF must drive outputs through an external output port. The generic output buffer (OBUF) symbol appears in Figure 37. OBUF I DS001_38_061200 Figure 37: Output Buffer (OBUF) Symbol The extension to the base name defines which I/O ...
Page 41
Spartan-II 2.5V FPGA Family: Functional Description <slew_rate> can be either F (Fast (Slow) and <drive_strength> is specified in milliamps ( 12, 16, or 24). IOBUFT DS001_39_032300 Figure 38: 3-State Output Buffer Symbol ...
Page 42
R The following list details variations of the IOBUF symbol: • IOBUF • IOBUF_S_2 • IOBUF_S_4 • IOBUF_S_6 • IOBUF_S_8 • IOBUF_S_12 • IOBUF_S_16 • IOBUF_S_24 • IOBUF_F_2 • IOBUF_F_4 • IOBUF_F_6 • IOBUF_F_8 • IOBUF_F_12 • IOBUF_F_16 • IOBUF_F_24 ...
Page 43
Spartan-II 2.5V FPGA Family: Functional Description Output Slew Rate Property As mentioned above, a variety of symbol names provide the option of choosing the desired slew rate for the output buff- ers. In the case of the LVTTL output buffers ...
Page 44
R These termination techniques can be applied in any combi- nation. A generic example of each combination of termina- tion methods appears in Figure 40. Unterminated Double Parallel Terminated Z=50 Unterminated Output Driving Series Terminated Output Driving a Parallel Terminated ...
Page 45
Spartan-II 2.5V FPGA Family: Functional Description Table 18: Effective Output Power/Ground Pairs for Spartan-II Devices Spartan-II Devices XC2S XC2S XC2S Pkg VQ100 CS144 TQ144 PQ208 - 16 16 ...
Page 46
R GTL+ A sample circuit illustrating a valid termination technique for GTL+ appears in Figure 42. DC voltage specifications appear in Table 20 . GTL 1.5V TT 50Ω CCO REF Figure ...
Page 47
Spartan-II 2.5V FPGA Family: Functional Description HSTL Class III A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 44. DC voltage specifications appear in Table 22. HSTL Class III V = 1.5V CCO ...
Page 48
R SSTL3 Class I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 46. DC voltage specifications appear in Table 24. SSTL3 Class 3.3V CCO 25Ω REF Figure 46: ...
Page 49
Spartan-II 2.5V FPGA Family: Functional Description SSTL2_I A sample circuit illustrating a valid termination technique for SSTL2_I appears in Figure 48. DC voltage specifications appear in Table 26 SSTL2 Class 2.5V CCO 25Ω ...
Page 50
R CTT A sample circuit illustrating a valid termination technique for CTT appear in Figure 50. DC voltage specifications appear in Table 28 . CTT V = 3.3V CCO REF Figure 50: Terminated CTT Table 28: ...
Page 51
Spartan-II 2.5V FPGA Family: Functional Description LVTTL LVTTL requires no termination. DC voltage specifications appears in Table 31. Table 31: LVTTL Voltage Specifications Parameter Min V 3.0 CCO V - REF 2 –0.5 IL ...
Page 52
R Revision History Date Version 09/18/00 2.0 Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description. 03/05/01 2.1 Clarified guidelines for applying power to V 09/03/03 2.2 The following changes were made: • Serial Modes, page 14 ...
Page 53
Spartan-II 2.5V FPGA Family: Functional Description Module www.xilinx.com 1-800-255-7778 R DS001-2 (v2.2) September 3, 2003 Product Specification ...
Page 54
... For soldering guidelines, see the Packaging Information on the Xilinx web site: http://www.xilinx.com/publications/products/packaging/index.htm © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...
Page 55
... I/O standard selected. CCO . CCO Description voltage (below which configuration data voltage (below which configuration data may (1) XC2S15 Commercial Industrial XC2S30 Commercial Industrial XC2S50 Commercial Industrial XC2S100 Commercial Industrial XC2S150 Commercial Industrial XC2S200 Commercial Industrial (1) pin (2) ...
Page 56
R Power-On Requirements Spartan-II FPGAs require that a minimum supply current I be provided to the V CCPO CCINT power-on. If more current is available, the FPGA can con- sume more than I minimum, though this cannot CCPO adversely affect ...
Page 57
... All timing parameters assume worst-case operating condi- tions (supply voltage and junction temperature). Values apply to all Spartan-II devices unless otherwise noted. Device All Constants for Calculating T 11. Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Constants for Calculating T 11. www.xilinx.com 1-800-255-7778 ...
Page 58
... Standard Global Clock Input Adjustments, page DS001-3 (v2.7) September 3, 2003 Product Specification Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Device All 1 (1) IOB Input Delay Adjustments for 11. Device XC2S15 2 XC2S30 2 (1) XC2S50 2 XC2S100 2 XC2S150 2 XC2S200 2 IOB Input Delay Adjustments for 11. www.xilinx.com 1-800-255-7778 Speed Grade -6 -5 Min ...
Page 59
... A zero hold time listing indicates no hold time or a negative hold time. Module (1) Description Device All All All XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 All (2) All (1) XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 All All All All www.xilinx.com 1-800-255-7778 7. Speed Grade -6 -5 Min Max Min - 0 ...
Page 60
R IOB Input Delay Adjustments for Different Standards Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit. Symbol Description ...
Page 61
Spartan-II 2.5V FPGA Family: DC and Switching Characteristics IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown ...
Page 62
R IOB Output Delay Adjustments for Different Standards Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. A delay adjusted in ...
Page 63
Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Calculation Function of IOOP Capacitance T is the propagation delay from the O Input of the IOB IOOP to the pad. The values for T are based on ...
Page 64
R Clock Distribution Guidelines Symbol GCLK Clock Skew T Global clock skew between IOB flip-flops GSKEWIOB Notes: 1. These clock distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case conditions. Precise ...
Page 65
Spartan-II 2.5V FPGA Family: DC and Switching Characteristics DLL Timing Parameters Switching parameters testing is modeled after testing meth- ods specified by MIL-M-38510/605; all devices are 100 per- cent functionally tested. Because of the difficulty in directly measuring many internal ...
Page 66
R Period Tolerance: the allowed input clock period change in nanoseconds CLKIN F CLKIN Output Jitter: the difference between an ideal reference clock edge and the actual design. Ideal Period Actual Period DS001-3 (v2.7) September 3, 2003 Product ...
Page 67
Spartan-II 2.5V FPGA Family: DC and Switching Characteristics CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Symbol Combinatorial Delays ...
Page 68
R CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Symbol Combinatorial Delays T F operand inputs to ...
Page 69
Spartan-II 2.5V FPGA Family: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics Symbol Sequential Delays T Clock CLK to X/Y outputs (WE active mode) SHCKO16 T Clock CLK to X/Y outputs (WE active ...
Page 70
R Block RAM Switching Characteristics Symbol Sequential Delays T Clock CLK to DOUT output BCKO Setup/Hold Times with Respect to Clock CLK ADDR inputs BACK BCKA DIN inputs BDCK BCKD ...
Page 71
... Removed Power Down feature. 01/19/01 2.2 DC and timing numbers updated to Preliminary for the XC2S50 and XC2S100. Industrial power-on current specifications and -6 DLL timing numbers added. Power-on specification clarified. 03/09/01 2.3 Added note on power sequencing. Clarified power-on current requirement. ...
Page 72
... IRDY, TRDY No © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS001-4 (v2.5) September 3, 2003 ...
Page 73
Spartan-II 2.5V FPGA Family: Pinout Tables Pinout Tables The following device-specific pinout tables include all packages available for each Spartan-II device. They follow the pad locations around the die, and include Boundary Scan register locations. XC2S15 Device Pinouts XC2S15 Pad ...
Page 74
R XC2S15 Device Pinouts (Continued) XC2S15 Pad Name Function Bank VQ100 TQ144 I/O (D6) 3 P56 GND - - I/O (D5) 3 P57 I/O 3 P58 I/ P59 REF I/O (D4) 3 P60 I ...
Page 75
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S30 Device Pinouts XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 GND - P1 P143 TMS - P2 P142 I P141 I P140 I I/O, V ...
Page 76
R XC2S30 Device Pinouts (Continued) XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 P84 I P83 V - P42 P82 CCINT CCO ...
Page 77
... D5 P198 - Notes: A4 P199 86 1. For the PQ208 package, P13, P38, P118, and P143, which are Not Connected Pins on the XC2S30, are assigned to B4 P200 89 V CCINT XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Bndry Function FG256 Scan I/O P1 GND 149 www ...
Page 78
... I/ P122 P31 REF GND - - P32 I P33 I P34 I P35 I I/O 6 P121 P36 DS001-4 (v2.5) September 3, 2003 Product Specification XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Bndry FG256 Scan Function P5 D2 161 I/O - GND CCINT P6 C1 164 V CCO P7 F3 167 GND - E2 170 I 173 ...
Page 79
... P95 I/O 4 P78 P96 I I P97 I/ P77 P98 REF GND - - I P99 I I/O 4 P76 P100 Module XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Bndry FG256 Scan Function M7 332 I/O N7 338 I/O T6 341 I/O P7 344 GND GND* - DONE P8 347 V CCO R7 350 V CCO - T7 353 T8 356 ...
Page 80
... P35 P156 CCO TDO 2 P34 P157 GND - P33 P158 TDI - P32 P159 I/O (CS) 1 P31 P160 DS001-4 (v2.5) September 3, 2003 Product Specification XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Bndry FG256 Scan Function V - I/O (WRITE) CCO Bank 2* I/O GND* - I/O H16 515 I/O H14 518 I/O H15 521 ...
Page 81
... Spartan-II 2.5V FPGA Family: Pinout Tables XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Function Bank TQ144 PQ208 I P193 I/O 0 P11 P194 I/O 0 P10 P195 P196 CCINT P197 CCO GND - P8 P198 I P199 I P200 I P201 I I P202 I/ P203 REF GND - - I P204 ...
Page 82
R XC2S100 Device Pinouts XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 GND - P143 P1 TMS - P142 P2 I/O 7 P141 P3 I I/O 7 P140 ...
Page 83
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 I/O 5 P103 P57 P58 GND - - - V 5 ...
Page 84
R XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 GND - - - CCO I/ P65 P111 REF I P112 I I/O 3 P64 P113 ...
Page 85
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 CCO I/ P28 P164 REF I P165 I I ...
Page 86
R Additional XC2S100 Package Pins TQ144 Not Connected Pins P104 P105 - - 11/02/00 PQ208 Not Connected Pins P55 P56 - - 11/02/00 FG256 V Pins CCINT C3 C14 D4 D13 M5 M12 N4 N13 V Bank 0 Pins CCO ...
Page 87
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts XC2S150 Pad Name Function Bank PQ208 FG256 GND - P1 GND* TMS - GND - - GND* I/O ...
Page 88
R XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 I/O 6 P46 I/O 6 P47 GND - - GND ...
Page 89
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 I/O 4 P90 V - P91 V CCINT V 4 P92 V CCO Bank 4* GND - P93 GND* I/O 4 P94 I/O, ...
Page 90
R XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 (1) I/O, IRDY 2 P132 I/O 2 P133 I I/O 2 P134 I I/O (D3) 2 P135 I/ P136 REF V 2 ...
Page 91
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 I/O 1 P174 I I/O 1 P175 I/O 1 P176 GND - P177 GND CCO Bank 1* ...
Page 92
R Additional XC2S150 Package Pins PQ208 Not Connected Pins P55 P56 - - 11/02/00 FG256 V Pins CCINT C3 C14 D4 D13 M5 M12 N4 N13 V Bank 0 Pins CCO Bank 1 Pins CCO ...
Page 93
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts XC2S200 Pad Name Function Bank PQ208 FG256 GND - P1 GND* TMS - GND - - GND* I/O, ...
Page 94
R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 I I/O 6 P43 GND - - GND I/O 6 P44 I/ P45 REF V ...
Page 95
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 I, GCK0 4 P80 I/O 4 P81 I I/O 4 P82 I I I/O 4 P83 I/O, ...
Page 96
R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 V 3 P117 V CCO Bank P118 V CCINT I/O (D5) 3 P119 I/O 3 P120 ...
Page 97
Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 V 1 P156 V CCO Bank 1* TDO 2 P157 GND - P158 GND* TDI - P159 I/O (CS) 1 P160 I/O (WRITE) ...
Page 98
R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 GND - P198 GND* I/O 0 P199 I/ P200 REF I I/O 0 P201 GND - - GND ...
Page 99
... Removed the Power Down feature. 2.3 03/05/01 Added notes on pinout tables for IRDY and TRDY. 2.4 04/30/01 Reinstated XC2S50 V 2.5 09/03/03 Added caution about Not Connected Pins to XC2S30 pinout tables on The Spartan-II Family Data Sheet DS001-1, Spartan-II 2.5V FPGA Family: DS001-2, Spartan-II 2.5V FPGA Family: DS001-3, Spartan-II 2.5V FPGA Family: DS001-4, Spartan-II 2 ...