XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 28

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL applica-
tion as shown in
This symbol does not provide access to the advanced clock
domain controls or to the clock multiplication or clock divi-
sion features of the DLL. This symbol also does not provide
access to the RST, or LOCKED pins of the DLL. For access
to these features, a designer must use the library DLL prim-
itives described in the following sections.
Source Clock Input — I
The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the BUF-
GDLL macro the source clock frequency must fall in the low
frequency range as specified in the data sheet. The BUF-
GDLL requires an external signal source clock. Therefore,
only an external input port can source the signal that drives
the BUFGDLL I pin.
Clock Output — O
The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced by
a global clock buffer BUFG symbol, takes advantage of the
dedicated global clock routing resources of the device.
The output clock has a 50/50 duty cycle unless you deacti-
vate the duty cycle correction property.
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the com-
plete set of DLL features needed when implementing more
complex applications with the DLL.
Source Clock Input — CLKIN
The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL
DS001-2 (v2.2) September 3, 2003
Product Specification
I
IBUFG
R
O
Figure 24: BUFGDLL Schematic
Figure
CLKIN
CLKFB
RST
CLKDLL
24.
LOCKED
CLK180
CLK270
CLKDV
CLK2X
CLK90
CLK0
I
BUFG
O
DS001_25_032300
www.xilinx.com
1-800-255-7778
or one of the global clock input buffers (IBUFG) must source
this clock signal.
Feedback Clock Input — CLKFB
The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. The feed-
back clock input can also be provided through one of the fol-
lowing pin.
If an IBUFG sources the CLKFB pin, the following special
rules apply.
1. An external input port must source the signal that drives
2. The CLK2X output must feed back to the device if both
3. That signal must directly drive only OBUFs and nothing
These rules enable the software determine which DLL clock
output sources the CLKFB pin.
Reset Input — RST
When the reset pin RST activates the LOCKED signal deac-
tivates within four source clock cycles. The RST pin, active
High, must either connect to a dynamic signal or tied to
ground. As the DLL delay taps reset to zero, glitches can
occur on the DLL clock output pins. Activation of the RST
pin can also severely affect the duty cycle of the clock out-
put pins. Furthermore, the DLL output clocks no longer
deskew with respect to one another. For these reasons,
rarely use the reset pin unless re-configuring the device or
changing the input frequency.
2x Clock Output — CLK2X
The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the
CLKDLLHF primitive.
Clock Divide Output — CLKDV
The clock divide output pin CLKDV provides a lower fre-
quency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
This feature provides automatic duty cycle correction such
that the CLKDV output pin always has a 50/50 duty cycle.
1x Clock Outputs — CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a delay-compen-
sated version of the source clock (CLKIN) signal. The
Spartan-II 2.5V FPGA Family: Functional Description
IBUFG - Global Clock Input Pad
the IBUFG I pin.
the CLK0 and CLK2X outputs are driving off chip
devices.
else.
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