XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 72

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

DS001-4 (v2.5) September 3, 2003
Pin Definitions
DS001-4 (v2.5) September 3, 2003
Product Specification
GCK0, GCK1, GCK2,
GCK3
M0, M1, M2
CCLK
PROGRAM
DONE
INIT
BUSY/DOUT
D0/DIN, D1, D2, D3, D4,
D5, D6, D7
WRITE
CS
TDI, TDO, TMS, TCK
V
V
V
GND
IRDY, TRDY
CCINT
CCO
REF
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Pin Name
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Dedicated
R
Pin
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Input
Input
Input or Output
Input
Bidirectional
Bidirectional
(Open-drain)
Output
Input or Output
Input
Input
Mixed
Input
Input
Input
Input
See PCI core
documentation
Direction
028
0
www.xilinx.com
1-800-255-7778
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
Mode pins are used to specify the configuration mode.
The configuration Clock I/O pin. It is an input for slave-parallel and
slave-serial modes, and output in master-serial mode.
Initiates a configuration sequence when asserted Low.
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output may be open drain.
When Low, indicates that the configuration memory is being cleared. This
pin becomes a user I/O after configuration.
In Slave Parallel mode, BUSY controls the rate at which configuration data
is loaded. This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to downstream devices
in a daisy-chain. This pin becomes a user I/O after configuration.
In Slave Parallel mode, D0-D7 are configuration data input pins. During
readback, D0-D7 are output pins. These pins become user I/Os after
configuration unless the Slave Parallel port is retained.
In serial modes, DIN is the single data input. This pin becomes a user I/O
after configuration.
In Slave Parallel mode, the active-low Write Enable signal. This pin
becomes a user I/O after configuration unless the Slave Parallel port is
retained.
In Slave Parallel mode, the active-low Chip Select signal. This pin
becomes a user I/O after configuration unless the Slave Parallel port is
retained.
Boundary Scan Test Access Port pins (IEEE 1149.1).
Power supply pins for the internal core logic.
Power supply pins for output drivers (subject to banking rules)
Input threshold voltage pins. Become user I/Os when an external threshold
voltage is not needed (subject to banking rules).
Ground.
These signals can only be accessed when using Xilinx PCI cores. If the
cores are not used, these pins are available as user I/Os.
0
Spartan-II 2.5V FPGA Family:
Pinout Tables
Product Specification
Description
Module 4 of 4
1