XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 14

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Global Routing
Global Routing resources distribute clocks and other sig-
nals with very high fanout throughout the device. Spartan-II
devices include two tiers of global routing resources
referred to as primary and secondary global routing
resources.
•
•
Clock Distribution
The Spartan-II family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Figure
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the gen-
eral purpose routing. Global clock pins do not have the
option for internal, weak pull-up resistors.
DS001-2 (v2.2) September 3, 2003
Product Specification
Global
Clock Rows
The primary global routing resources are four
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets may only be driven by global buffers. There are
four global buffers, one for each global net.
The secondary global routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
Figure 7: Global Clock Distribution Network
7.
R
GCLKBUF1
GCLKPAD1
GCLKBUF3
GCLKPAD3
GCLKBUF0
GCLKPAD0
GCLKPAD2
GCLKBUF2
DS001_08_060100
Global Clock
Column
Global Clock
Spine
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Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully digi-
tal Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks. The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element.
Additional delay is introduced such that clock edges reach
internal flip-flops exactly one clock period after they arrive at
the input. This closed-loop system effectively eliminates
clock-distribution delay by ensuring that clock edges arrive
at internal flip-flops in synchronism with clock edges arriving
at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. It has six outputs.
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to deskew a board level clock among multiple Spar-
tan-II devices.
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
DLL can delay the completion of the configuration process
until after it has achieved lock.
Boundary Scan
Spartan-II devices support all the mandatory bound-
ary-scan instructions specified in the IEEE standard 1149.1.
A Test Access Port (TAP) and registers are provided that
implement the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP also supports two USERCODE
instructions and internal scan chains.
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the V
Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail
between ground and V
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including unbonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
Table 6
Spartan-II FPGAs. Internal signals can be captured during
EXTEST by connecting them to unbonded or unused IOBs.
They may also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Spartan-II 2.5V FPGA Family: Functional Description
lists the boundary-scan instructions supported in
CCO
.
Module 2 of 4
CCO
for
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