XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 13

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
•
General Purpose Routing
Most Spartan-II signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. The general routing resources are located in horizon-
tal and vertical routing channels associated with the rows
and columns CLBs. The general-purpose routing resources
are listed below.
•
•
Module 2 of 4
6
Adjacent
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
24 single-length lines route GRM signals to adjacent
GRM
To
Direct Connection
CLB
Figure 5: Spartan-II Local Routing
To Adjacent
To Adjacent
To Adjacent
GRM
GRM
GRM
CLB
Figure 6: BUFT Connections to Dedicated Horizontal Bus Lines
To Adjacent
GRM
CLB
CLB
DS001_06_032300
Direct
Connection
To Adjacent
CLB
www.xilinx.com
1-800-255-7778
•
•
I/O Routing
Spartan-II devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the VersaRing,
facilitates pin-swapping and pin-locking, such that logic
redesigns can adapt to existing PCB layouts. Time-to-mar-
ket is reduced, since PCBs and other system components
can be manufactured while the logic design is still in
progress.
Dedicated Routing
Some classes of signal require dedicated routing resources
to maximize performance. In the Spartan-II architecture,
dedicated routing resources are provided for two classes of
signal.
•
•
CLB
GRMs in each of the four directions.
96 buffered Hex lines route GRM signals to other
GRMs six blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are unidirectional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
DS001-2 (v2.2) September 3, 2003
CLB
Figure
6.
Product Specification
DS001_07_090600
3-State
Lines
R