XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 30

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

The LOC property uses the following form.
Design Factors
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Input Clock
The output clock signal of a DLL, essentially a delayed ver-
sion of the input clock signal, reflects any instability on the
input clock in the output waveform. For this reason the qual-
ity of the DLL input clock relates directly to the quality of the
output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the data sheet.
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially available
quartz crystal oscillator. For example, most crystal oscilla-
tors produce an output waveform with a frequency tolerance
of 100 PPM, meaning 0.01 percent change in the clock
period. The DLL operates reliably on an input waveform with
a frequency drift of up to 1 ns — orders of magnitude in
excess of that needed to support any crystal oscillator in the
industry. However, the cycle-to-cycle jitter must be kept to
less than 300 ps in the low frequencies and 150 ps for the
high frequencies.
Input Clock Changes
Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL will produce an unreliable lock signal and
output clock.
It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100 µs to keep device cooling to a minimum. The clock
should be stopped during a Low phase, and when restored
DS001-2 (v2.2) September 3, 2003
Product Specification
LOC = DLL2
GCLKBUF3
GCLKPAD1
GCLKBUF1
GCLKPAD3
R
DLL3
DLL1
Figure 26: Orientation of DLLs
DLL0
DLL2
GCLKBUF0
GCLKPAD2
GCLKBUF2
GCLKPAD0
DS001_27_032300
www.xilinx.com
1-800-255-7778
the full High period should be seen. During this time
LOCKED will stay High and remain High when the clock is
restored.
When the clock is stopped, one to four more clocks will still
be observed as the delay line is flushed. When the clock is
restarted, the output clocks will not be observed for one to
four clocks as the delay line is filled. The most common
case will be two or three clocks.
In a similar manner, a phase shift of the input clock is also
possible. The phase shift will propagate to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control.
Output Clocks
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or they can route directly to destination
clock pins. The only BUFGs that the DLL clock outputs can
drive are the two on the same edge of the device (top or bot-
tom).
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
Useful Application Examples
The Spartan-II DLL can be used in a variety of creative and
useful applications. The following examples show some of
the more common applications.
Standard Usage
The circuit shown in
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
Deskew of Clock and Its 2x Multiple
The circuit shown in
plier and also uses the CLK0 clock output with zero ns skew
between registers on the same chip. A clock divider circuit
Spartan-II 2.5V FPGA Family: Functional Description
Figure 27: Standard DLL Implementation
IBUFG
IBUF
CLKIN
CLKFB
RST
Figure 28
Figure 27
CLKDLL
LOCKED
CLK180
CLK270
CLKDV
CLK2X
CLK90
CLK0
implements a 2x clock multi-
resembles the BUFGDLL
BUFG
OBUF
DS001_28_061200
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