XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 15

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
Table 6: Boundary-Scan Instructions
Module 2 of 4
8
Boundary-Scan
RESERVED
USRCODE
Command
CFG_OUT
SAMPLE
EXTEST
IDCODE
BYPASS
CFG_IN
INTEST
JSTART
USR1
USR2
HIZ
Code[4:0]
All other
Binary
00000
00001
00010
00011
00100
00101
00111
01000
01001
01010
01100
11111
codes
Enables boundary-scan
Enables boundary-scan
Enables boundary-scan
Enables shifting out of
Access user-defined
Access user-defined
configuration bus for
configuration bus for
Disables output pins
Enables shifting out
SAMPLE operation
EXTEST operation
INTEST operation
while enabling the
StartupClk is TCK
Clock the start-up
Enables BYPASS
Bypass Register
sequence when
Xilinx reserved
Configuration
Description
USER code
instructions
Access the
Access the
Readback
register 1
register 2
ID Code
www.xilinx.com
1-800-255-7778
The public boundary-scan instructions are available prior to
configuration. After configuration, the public instructions
remain available together with any USERCODE instructions
installed during the configuration. While the SAMPLE and
BYPASS instructions are available during configuration, it is
recommended that boundary-scan operations not be per-
formed during this transitional period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
To facilitate internal scan chains, the User Register provides
three outputs (Reset, Update, and Shift) that represent the
corresponding states in the boundary-scan internal state
machine.
Figure 8
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.
is a diagram of the Spartan-II family boundary scan
DS001-2 (v2.2) September 3, 2003
Product Specification
R