XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 20

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Notes: (referring to waveform above:)
1.
Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low. At this time, the user can
delay configuration by holding either PROGRAM or INIT
Low, which causes the device to remain in the memory
clearing phase. Note that the bidirectional INIT line is driv-
ing a Low logic level during memory clearing. Thus, to avoid
contention, use an open-drain driver to keep INIT Low.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the con-
figuration data are discussed in the sections treating the
configuration modes individually. The sequence of opera-
tions necessary to load configuration data using the serial
modes is shown in
Parallel mode is shown in
CRC Error Checking
During the loading of configuration data, a CRC value
embedded in the configuration file is checked against a
CRC value calculated within the FPGA. If the CRC values
DS001-2 (v2.2) September 3, 2003
Product Specification
Before configuration can begin, V
R
.
PROGRAM
T
T
T
T
Figure
POR
PL
ICCK
PROGRAM
Symbol
V
INIT
CC
Figure 18, page
13. Loading data using the Slave
(1)
Power-on reset
Program latency
CCLK output delay (Master Serial
mode only)
Program pulse width
CCINT
Figure 11: Configuration Timing on Power-Up
must be greater than 1.6V and V
18.
Description
CCLK Output or Input
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T
POR
M0, M1, M2
(Required)
do not match, the FPGA drives INIT Low to indicate that a
frame error has occurred and configuration is aborted.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See
figuration
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the config-
uration data, initiates the sequence.
During start-up, the device performs four operations:
1. The assertion of DONE. The failure of DONE to go High
2. The release of the Global Three State net. This
3. Negates Global Set Reset (GSR). This allows all
4. The assertion of Global Write Enable (GWE). This
T
PL
Spartan-II 2.5V FPGA Family: Functional Description
may indicate the unsuccessful loading of configuration
data.
activates I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-down resistors present.
flip-flops to change state.
allows all RAMs and flip-flops to change state.
CCO
Bank 2 must be greater than 1.0V.
Memory.
100
300
0.5
2
4
T
ICCK
Valid
DS001_12_102301
ms, max
µ
µ
ns, min
µ
Units
s, max
s, max
s, min
Clearing Con-
Module 2 of 4
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