XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 44

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

These termination techniques can be applied in any combi-
nation. A generic example of each combination of termina-
tion methods appears in
Simultaneous Switching Guidelines
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Table 17
of simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce.
Refer to
DS001-2 (v2.2) September 3, 2003
Product Specification
Figure 40: Overview of Standard Input and Output
Unterminated Output Driving
a Parallel Terminated Input
Series Terminated Output
Unterminated
provides the guidelines for the maximum number
Table 18
R
Z=50
Z=50
Z=50
V
V
REF
REF
Termination Methods
V
for the number of effective output
TT
Figure
Driving a Parallel Terminated Input
Series-Parallel Terminated Output
Series Terminated Output Driving
Double Parallel Terminated
40.
a Parallel Terminated Input
V
V
TT
TT
Z=50
Z=50
Z=50
V
V
V
REF
REF
REF
DS001_41_032300
V
V
V
TT
TT
TT
www.xilinx.com
1-800-255-7778
power/ground pairs for each Spartan-II device and package
combination.
Table 17: Maximum Number of Simultaneously
Switching Outputs per Power/Ground Pair
Notes:
1.
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVCMOS2
PCI
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
CTT
AGP
Spartan-II 2.5V FPGA Family: Functional Description
This analysis assumes a 35 pF load for each output.
Standard
CS, FG
68
41
29
22
17
14
40
24
17
13
10
10
18
15
10
11
14
9
8
5
8
4
4
9
5
7
9
Package
Module 2 of 4
TQ, VQ
PQ,
36
20
15
12
21
12
9
7
5
9
7
5
4
3
5
4
4
4
9
5
3
8
5
6
4
7
5
37