XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 38

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

PCI — Peripheral Component Interface
The Peripheral Component Interface (PCI) standard speci-
fies support for both 33 MHz and 66 MHz PCI bus applica-
tions. It uses a LVTTL input buffer and a push-pull output
buffer. This standard does not require the use of a reference
voltage (V
ever, it does require a 3.3V output source voltage (V
I/Os configured for the PCI, 33 MHz, 5V standard are also
5V-tolerant.
GTL — Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic (GTL) standard is a
high-speed bus standard (JESD8.3) invented by Xerox. Xil-
inx has implemented the terminated variation of this stan-
dard. This standard requires a differential amplifier input
buffer and an open-drain output buffer.
GTL+ — Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus (GTL+) standard is a
high-speed bus standard (JESD8.3) first used by the Pen-
tium Pro processor.
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic (HSTL) standard is a
general purpose high-speed, 1.5V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. Versatile I/O devices support Class I, III, and IV.
This standard requires a Differential Amplifier input buffer
and a Push-Pull output buffer.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V (SSTL3) stan-
dard is a general purpose 3.3V memory bus standard also
sponsored by Hitachi and IBM (JESD8-8). This standard
has two classes, I and II. Versatile I/O devices support both
classes for the SSTL3 standard. This standard requires a
Differential Amplifier input buffer and an Push-Pull output
buffer.
SSTL2 — Stub Series Terminated Logic for 2.5V
The Stub Series Terminated Logic for 2.5V (SSTL2) stan-
dard is a general purpose 2.5V memory bus standard spon-
sored by Hitachi and IBM (JESD8-9). This standard has two
classes, I and II. Versatile I/O devices support both classes
for the SSTL2 standard. This standard requires a Differen-
tial Amplifier input buffer and an Push-Pull output buffer.
CTT — Center Tap Terminated
The Center Tap Terminated (CTT) standard is a 3.3V mem-
ory bus standard sponsored by Fujitsu (JESD8-4). This
standard requires a Differential Amplifier input buffer and a
Push-Pull output buffer.
AGP-2X — Advanced Graphics Port
The Intel AGP standard is a 3.3V Advanced Graphics
Port-2X bus standard used with the Pentium II processor for
DS001-2 (v2.2) September 3, 2003
Product Specification
REF
R
) or a board termination voltage (V
TT
), how-
www.xilinx.com
CCO
1-800-255-7778
).
graphics applications. This standard requires a Push-Pull
output buffer and a Differential Amplifier input buffer.
Library Symbols
The Xilinx library includes an extensive list of symbols
designed to provide support for the variety of Versatile I/O
features. Most of these symbols represent variations of the
five generic Versatile I/O symbols:
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•
•
•
•
IBUF
Signals used as inputs to the Spartan-II device must source
an input buffer (IBUF) via an external input port. The generic
IBUF symbol appears in
base name defines which I/O standard the IBUF uses. The
assumed standard is LVTTL when the generic IBUF has no
specified extension.
The following list details the variations of the IBUF symbol:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
When the IBUF symbol supports an I/O standard such as
LVTTL, LVCMOS, or PCI33_5, the IBUF automatically con-
figures as a 5V tolerant input buffer unless the V
bank is less than 2V. If the single-ended IBUF is placed in a
Spartan-II 2.5V FPGA Family: Functional Description
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
IBUF
IBUF_LVCMOS2
IBUF_PCI33_3
IBUF_PCI33_5
IBUF_PCI66_3
IBUF_GTL
IBUF_GTLP
IBUF_HSTL_I
IBUF_HSTL_III
IBUF_HSTL_IV
IBUF_SSTL3_I
IBUF_SSTL3_II
IBUF_SSTL2_I
IBUF_SSTL2_II
IBUF_CTT
IBUF_AGP
Figure 34: Input Buffer (IBUF) Symbols
I
Figure
IBUF
DS001_35_061200
34. The extension to the
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