XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 42

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

The following list details variations of the IOBUF symbol:
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When the IOBUF symbol supports an I/O standard such as
LVTTL, LVCMOS, or PCI33_5, the IBUF automatically con-
figures as a 5V tolerant input buffer unless the V
bank is less than 2V. If the single-ended IBUF is placed in a
bank with an HSTL standard (V
not 5V tolerant.
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all pack-
ages there are eight independent V
See
tan-II I/O banks. Within each bank approximately one of
every six I/O pins is automatically configured as a V
input.
Additional restrictions on the Versatile I/O IOBUF placement
require that within a given V
share the same output source drive voltage. Input buffers of
any type and output buffers that do not require V
placed within the same V
specify a location for the IOBUF.
DS001-2 (v2.2) September 3, 2003
Product Specification
IOBUF
IOBUF_S_2
IOBUF_S_4
IOBUF_S_6
IOBUF_S_8
IOBUF_S_12
IOBUF_S_16
IOBUF_S_24
IOBUF_F_2
IOBUF_F_4
IOBUF_F_6
IOBUF_F_8
IOBUF_F_12
IOBUF_F_16
IOBUF_F_24
IOBUF_LVCMOS2
IOBUF_PCI33_3
IOBUF_PCI33_5
IOBUF_PCI66_3
IOBUF_GTL
IOBUF_GTLP
IOBUF_HSTL_I
IOBUF_HSTL_III
IOBUF_HSTL_IV
IOBUF_SSTL3_I
IOBUF_SSTL3_II
IOBUF_SSTL2_I
IOBUF_SSTL2_II
IOBUF_CTT
IOBUF_AGP
Figure 35, page 32
R
for a representation of the Spar-
CCO
CCO
bank. The LOC property can
CCO
bank each IOBUF must
< 2V), the input buffer is
REF
banks internally.
CCO
CCO
can be
for the
www.xilinx.com
1-800-255-7778
REF
An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.
In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal, acti-
vate the delay element with the DELAY=TRUE property.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak "keeper" circuit. Control this feature by adding the
appropriate symbol to the output net of the IOBUF
(PULLUP, PULLDOWN, or KEEPER).
Versatile I/O Properties
Access to some of the Versatile I/O features (for example,
location constraints, input delay, output drive strength, and
slew rate) is available through properties associated with
these features.
Input Delay Properties
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to over-
ride this default.
In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to pro-
vide higher performance. To delay the input signal, activate
the delay element with the DELAY=TRUE property.
IOB Flip-Flop/Latch Property
The I/O Block (IOB) includes an optional register on the
input path, an optional register on the output path, and an
optional register on the 3-state control pin. The design
implementation software automatically takes advantage of
these registers when the following option for the Map pro-
gram is specified:
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
Location Constraints
Specify the location of each Versatile I/O symbol with the
location constraint LOC attached to the Versatile I/O sym-
bol. The external port identifier indicates the value of the
location constrain. The format of the port identifier depends
on the package chosen for the specific design.
The LOC properties use the following form:
Spartan-II 2.5V FPGA Family: Functional Description
LOC=A42
LOC=P37
map -pr b <filename>
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