XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 29

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
CLKDLL primitive provides three phase-shifted versions of
the CLK0 signal while CLKDLLHF provides only the 180
phase-shifted version. The relationship between phase shift
and the corresponding period shift appears in
The timing diagrams in
output characteristics.
Table 9: Relationship of Phase-Shifted Output Clock to
Period Shift
The DLL provides duty cycle correction on all 1x clock out-
puts such that all 1x clock outputs by default have a 50/50
duty cycle. The DUTY_CYCLE_CORRECTION property
(TRUE by default), controls this feature. In order to deacti-
vate
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
Locked Output — LOCKED
In order to achieve lock, the DLL may need to sample sev-
eral thousand clock cycles. After the DLL achieves lock the
LOCKED signal activates. The DLL timing parameter sec-
tion of the data sheet provides estimates for locking times.
In order to guarantee that the system clock is established
prior to the device "waking up," the DLL can delay the com-
pletion of the device configuration process until after the
DLL locks. The STARTUP_WAIT property activates this fea-
ture.
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spuri-
ous movement. In particular the CLK2X output will appear
as a 1x clock with a 25/75 duty cycle.
DLL Properties
Properties provide access to some of the Spartan-II family
DLL features, (for example, clock division and duty cycle
correction).
Duty Cycle Correction Property
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, exhibiting a 50/50 duty
cycle. The DUTY_CYCLE_CORRECTION property (by
default TRUE) controls this feature. To deactivate the DLL
Module 2 of 4
22
Phase (degrees)
the
180
270
DLL
90
0
duty
Figure 25
cycle
Period Shift (percent)
correction,
illustrate the DLL clock
25%
50%
75%
0%
Table
attach
9.
www.xilinx.com
1-800-255-7778
the
duty-cycle correction for the 1x clock outputs, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty-cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
Startup Delay Property
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the device con-
figuration DONE signal waits until the DLL locks before
going to High.
DLL Location Constraints
The DLLs are distributed such that there is one DLL in each
corner of the device. The location constraint LOC, attached
to the DLL symbol with the numeric identifier 0, 1, 2, or 3,
controls DLL location. The orientation of the four DLLs and
their corresponding clock resources appears in
CLKDV_DIVIDE = 2
DUTY_CYCLE_CORRECTION = FALSE
DUTY_CYCLE_CORRECTION = TRUE
CLK180
CLK270
CLK180
CLK270
CLKDV
CLK2X
CLK90
CLK90
CLKIN
CLK0
CLK0
Figure 25: DLL Output Characteristics
0
90 180 270
T
DS001-2 (v2.2) September 3, 2003
0
90 180 270
Product Specification
DS001_26_032300
Figure
26.
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