XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 10

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

I/O Banking
Some of the I/O standards described above require V
and/or V
nected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see
ple V
age. Voltage is determined by the output standards in use.
Within a bank, output standards may be mixed only if they
use the same V
Table
their open-drain outputs do not depend on V
Table 2: Compatible Output Standards
Some input standards require a user-supplied threshold
voltage, V
matically configured as inputs for the V
one in six of the I/O pins in the bank assume this role.
V
consequently only one V
DS001-2 (v2.2) September 3, 2003
Product Specification
REF
V
3.3V
2.5V
1.5V
CCO
CCO
2. GTL and GTL+ appear under all voltages because
pins within a bank are interconnected internally and
REF
pins which must be connected to the same volt-
REF
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
GTL, GTL+
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
R
voltages. These voltages are externally con-
Figure 2: Spartan-II I/O Banks
. In this case, certain user-I/O pins are auto-
Bank 0
Bank 5
CCO
. Compatible standards are shown in
GCLK3
GCLK1
Compatible Standards
Spartan-II
REF
Device
Figure
voltage can be used within
GCLK2
GCLK0
2). Each bank has multi-
Bank 1
Bank 4
REF
CCO
voltage. About
DS001_03_060100
.
www.xilinx.com
1-800-255-7778
CCO
each bank. All V
nected to the external voltage source for correct operation.
In a bank, inputs requiring V
that do not but only one V
bank. Input buffers that use V
LVTTL, LVCMOS2, and PCI are 5V tolerant. The V
V
Within a given package, the number of V
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
a superset of the V
possible to design a PCB that permits migration to a larger
device. All V
be connected to the V
Table 3: Independent Banks Available
Configurable Logic Block
The basic building block of the Spartan-II CLB is the logic
cell (LC). An LC includes a 4-input function generator, carry
logic, and storage element. Output from the function gener-
ator in each LC drives the CLB output and the D input of the
flip-flop. Each Spartan-II CLB contains four LCs, organized
in two similar slices; a single slice is shown in
In addition to the four basic LCs, the Spartan-II CLB con-
tains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-II function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.
The Spartan-II LUT can also provide a 16-bit shift register
that is ideal for capturing high-speed or burst-mode data.
This mode can also be used to store data in applications
such as Digital Signal Processing.
Storage Elements
Storage elements in the Spartan-II slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D inputs can be driven either by function
generators within the slice or directly from slice inputs,
bypassing the function generators.
Independent Banks
REF
Spartan-II 2.5V FPGA Family: Functional Description
pins for each bank appear in the device pinout tables.
Package
REF
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pins for the largest device anticipated must
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pins in the bank, however, must be con-
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pins used for smaller devices, it is
VQ100
PQ208
REF
REF
voltage, and not used for I/O.
1
REF
voltage may be used within a
pins. Since these are always
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can be mixed with those
are not 5V tolerant.
CS144
TQ144
REF
4
and V
Figure
Module 2 of 4
FG256
FG456
CCO
CCO
8
3.
pins
and
3