XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 17

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
Development System
Spartan-II FPGAs are supported by the Xilinx Foundation
and Alliance CAE tools. The basic methodology for Spar-
tan-II design consists of three interrelated steps: design
entry, implementation, and verification. Industry-standard
tools are used for design entry and simulation (for example,
Synopsys FPGA Express), while Xilinx provides proprietary
architecture-specific tools for implementation.
The Xilinx development system is integrated under the
Xilinx Design Manager software, providing designers with a
common user interface regardless of their choice of entry
and verification tools. The software simplifies the selection
of implementation options with pull-down menus and on-line
help.
Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
software. The program command sequence is generated
prior to execution, and stored for documentation.
Several advanced software features facilitate Spartan-II
design. Relationally-Placed Macros (RPMs), for example,
are schematic-based macros with relative location con-
straints to guide their placement. They help ensure optimal
implementation of common functions.
For HDL design entry, the Xilinx FPGA development system
provides interfaces to several synthesis design environ-
ments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Spartan-II FPGAs supported by a unified library of standard
functions. This library contains over 400 primitives and mac-
ros, ranging from 2-input AND gates to 16-bit accumulators,
and includes arithmetic functions, comparators, counters,
data registers, decoders, encoders, I/O functions, latches,
Module 2 of 4
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Bit 0 ( TDO end)
Bit 1
Bit 2
Figure 9: Boundary Scan Bit Sequence
(TDI end)
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MODE.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
DS001_10_032300
www.xilinx.com
1-800-255-7778
Boolean functions, multiplexers, shift registers, and barrel
shifters.
The "soft macro" portion of the library contains detailed
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor-
mance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.
RPMs, on the other hand, do contain predetermined parti-
tioning and placement information that permits optimal
implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.
The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchical design elements are auto-
matically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
design, thus allowing the most convenient entry method to
be used for each portion of the design.
Design Implementation
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The parti-
tioner takes the EDIF netlist for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their interconnec-
tions and the desired performance. Finally, the router inter-
connects the blocks.
The PAR algorithms support fully automatic implementation
of most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floorplanning.
The implementation software incorporates Timing Wizard
timing-driven placement and routing. Designers specify tim-
ing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
these user-specified requirements and accommodate them.
Timing requirements are entered on a schematic in a form
directly relating to the system requirements, such as the tar-
geted clock frequency, or the maximum allowable delay
between two registers. In this way, the overall performance
of the system along entire signal paths is automatically tai-
lored to user-generated specifications. Specific timing infor-
mation for individual nets is unnecessary.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
DS001-2 (v2.2) September 3, 2003
Product Specification
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