XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 69

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Module 3 of 4
16
Notes:
1.
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Clock CLK
Sequential Delays
Setup Times with Respect to Clock CLK
Clock CLK
T
T
T
T
T
T
A zero hold time listing indicates no hold time or a negative hold time.
Symbol
Symbol
T
WS
SHCKO16
SHCKO32
DS
AS
T
SHCECK
T
T
T
T
SHDICK
T
SRPH
SRPL
WPH
WPL
REG
WC
/ T
/ T
/ T
AH
DH
WH
Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
F/G address inputs
BX/BY data inputs (DIN)
CE input (WS)
Minimum pulse width, High
Minimum pulse width, Low
Minimum clock period to meet address write cycle time
Clock CLK to X/Y outputs
BX/BY data inputs (DIN)
CE input (WS)
Minimum pulse width, High
Minimum pulse width, Low
Description
Description
(1)
www.xilinx.com
1-800-255-7778
0.7 / 0
0.8 / 0
0.9 / 0
Min
Min
0.8
0.9
-
-
-
-
-
-
-
-
-6
-6
Max
Max
3.47
Speed Grade
Speed Grade
2.2
2.5
2.9
2.9
5.8
2.9
2.9
-
-
-
-
-
DS001-3 (v2.7) September 3, 2003
0.7 / 0
0.9 / 0
1.0 / 0
Min
Min
0.9
1.0
-
-
-
-
-
-
-
-
Product Specification
-5
-5
Max
Max
3.88
2.6
3.0
2.9
2.9
5.8
2.9
2.9
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R