XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 23

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
Master Serial Mode
In Master Serial mode, the CCLK output of the FPGA drives
a Xilinx PROM which feeds a serial stream of configuration
data to the FPGA’s DIN input.
Serial FPGA configuring a Slave Serial FPGA from a
PROM. A Spartan-II device in Master Serial mode should
be connected as shown for the device on the left side. Mas-
ter Serial mode is selected by a <00x> on the mode pins
(M0, M1, M2). The PROM RESET pin is driven by INIT, and
CE input is driven by DONE. The interface is identical to the
slave serial mode except that an oscillator internal to the
FPGA is used to generate the configuration clock (CCLK).
Any of a number of different frequencies ranging from 4 to
60 MHz can be set using the ConfigRate option in the Xilinx
development software. On power-up, while the first 60 bytes
Slave Parallel Mode
The Slave Parallel mode is the fastest configuration option.
Byte-wide data is written into the FPGA. A BUSY flag is pro-
vided for controlling the flow of data at a clock frequency
F
Figure 17, page 17
Spartan-II devices using the Slave Parallel mode. Slave
Parallel mode is selected by a <011> on the mode pins (M0,
M1, M2).
If a configuration file of the format .bit, .rbt, or non-swapped
HEX is used for parallel programming, then the most signif-
icant bit (i.e. the left-most bit of each configuration byte, as
Module 2 of 4
16
CCNH
above 50 MHz.
Serial Data In
Serial DOUT
.
T
T
Symbol
DSCK
CKDS
(Output)
(Output)
CCLK
shows the connections for two
CCLK
Figure 14
T
DSCK
DIN setup
DIN hold
Frequency tolerance with respect to
nominal
Figure 16: Master Serial Mode Timing
shows a Master
Description
www.xilinx.com
1-800-255-7778
T
T
CCO
CKDS
of the configuration data are being loaded, the CCLK fre-
quency is always 2.5 MHz. This frequency is used until the
ConfigRate bits, part of the configuration file, have been
loaded into the FPGA, at which point, the frequency
changes to the selected ConfigRate. Unless a different fre-
quency is specified in the design, the default ConfigRate is
4 MHz. The period of the CCLK signal created by the inter-
nal oscillator has a variance of +45%, –30% from the spec-
ified value.
Figure 16
The FPGA accepts one bit of configuration data on each ris-
ing CCLK edge. After the FPGA has been loaded, the data
for the next device in a daisy-chain is presented on the
DOUT pin after the rising CCLK edge.
displayed in a text editor) must be routed to the D0 input on
the FPGA.
The agent controlling configuration is not shown. Typically, a
processor, a microcontroller, or CPLD controls the Slave
Parallel interface. The controlling agent provides byte-wide
configuration data, CCLK, a Chip Select (CS) signal and a
Write signal (WRITE). If BUSY is asserted (High) by the
FPGA, the data must be held until BUSY goes Low.
After configuration, the pins of the Slave Parallel port
(D0-D7) can be used as additional user I/O. Alternatively,
the port may be retained to permit high-speed 8-bit read-
back. Then data can be read by de-asserting WRITE. See
Readback, page
shows the timing for Master Serial configuration.
+45%, –30%
18.
5.0
0.0
DS001-2 (v2.2) September 3, 2003
ns, min
ns, min
Units
DS001_17_110101
-
Product Specification
R