XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 36

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

At the third rising edge of CLKA, the T
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x7E is invalid.
At the fourth rising edge of CLKA, a read operation is per-
formed at memory location 0x0F and invalid data is present
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.
At the fifth rising edge of CLKA a read operation is per-
formed that does not violate the T
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
Initialization
The block RAM memory can initialize during the device con-
figuration sequence. The 16 initialization properties of 64
hex values each (a total of 4096 bits) set the initialization of
each RAM. These properties appear in
ization properties not explicitly set configure as zeros. Par-
tial initialization strings pad with zeros. Initialization strings
greater than 64 hex values generate an error. The RAMs
can be simulated with the initialization values using gener-
ics in VHDL simulators and parameters in Verilog simula-
tors.
Initialization in VHDL and Synopsys
The block RAM structures may be initialized in VHDL for
both simulation and synthesis for inclusion in the EDIF out-
put file. The simulation of the VHDL code uses a generic to
pass the initialization. Synopsys FPGA compiler does not
presently support generics. The initialization values instead
attach as attributes to the RAM by a built-in Synopsys
dc_script. The translate_off statement stops synthesis
translation of the generic statements. The following code
illustrates a module that employs these techniques.
Initialization in Verilog and Synopsys
The block RAM structures may be initialized in Verilog for
both simulation and synthesis for inclusion in the EDIF out-
put file. The simulation of the Verilog code uses a defparam
to pass the initialization. The Synopsys FPGA compiler
does not presently support defparam. The initialization val-
ues instead attach as attributes to the RAM by a built-in
Synopsys dc_script. The translate_off statement stops syn-
thesis translation of the defparam statements. The following
code illustrates a module that employs these techniques.
Block Memory Generation
The CoreGen program generates memory structures using
the block RAM features. This program outputs VHDL or Ver-
ilog simulation code templates and an EDIF file for inclusion
in a design.
DS001-2 (v2.2) September 3, 2003
Product Specification
R
BCCS
Table
BCCS
parameter to the
13. Any initial-
parameter is
www.xilinx.com
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Table 13: RAM Initialization Properties
Using Versatile I/O
The Spartan-II FPGA family includes a highly configurable,
high-performance I/O resource called Versatile I/O to pro-
vide support for a wide variety of I/O standards. The Versa-
tile I/O resource is a robust set of features including
programmable control of output drive strength, slew rate,
and input delay and hold time. Taking advantage of the flex-
ibility and Versatile I/O features and the design consider-
ations described in this document can improve and simplify
system level design.
Introduction
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for high-perfor-
mance I/O becomes more important. While chip-to-chip
delays have an increasingly substantial impact on overall
system speed, the task of achieving the desired system per-
formance becomes more difficult with the proliferation of
low-voltage I/O standards. Versatile I/O, the revolutionary
input/output resources of Spartan-II devices, has resolved
this potential problem by providing a highly configurable,
high-performance alternative to the I/O resources of more
conventional programmable devices. The Spartan-II Versa-
tile I/O features combine the flexibility and time-to-market
advantages of programmable logic with the high perfor-
Spartan-II 2.5V FPGA Family: Functional Description
Property
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0a
INIT_0b
INIT_0c
INIT_0d
INIT_0e
INIT_0f
Memory Cells
1279 to 1024
1535 to 1280
1791 to 1536
2047 to 1792
2303 to 2048
2559 to 2304
2815 to 2560
3071 to 2816
3327 to 3072
3583 to 3328
3839 to 3584
4095 to 3840
1023 to 768
511 to 256
767 to 512
255 to 0
Module 2 of 4
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