XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 37

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
mance previously available only with ASICs and custom
ICs.
Each Versatile I/O block can support up to 16 I/O standards.
Supporting such a variety of I/O standards allows the sup-
port of a wide variety of applications, from general purpose
standard applications to high-speed low-voltage memory
busses.
Versatile I/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL out-
put buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak "keeper" circuit ideal for
use in external bussing applications.
Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
The input buffer has an optional delay element used to guar-
antee a zero hold time requirement for input signals regis-
tered within the IOB.
The Versatile I/O features also provide dedicated resources
for input reference voltage (V
(V
fies board design.
By taking advantage of the built-in features and wide variety
of I/O standards supported by the Versatile I/O features,
system-level design and board design can be greatly simpli-
fied and improved.
Fundamentals
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored spe-
cifically to the needs of that application. The bus I/O stan-
dards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly depen-
dent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards
The Versatile I/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in
support a variety of voltage requirements.
Module 2 of 4
30
CCO
), along with a convenient banking system that simpli-
REF
Table
) and output source voltage
14, each buffer type can
www.xilinx.com
1-800-255-7778
Table 14: Versatile I/O Supported Standards (Typical
Values)
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards
supported by all Spartan-II devices.
While most I/O standards specify a range of allowed volt-
ages, this document records typical voltage values only.
Detailed information on each specification may be found on
the
http://www.jedec.org
LVTTL — Low-Voltage TTL
The Low-Voltage TTL (LVTTL) standard is a general pur-
pose EIA/JESDSA standard for 3.3V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
standard requires a 3.3V output source voltage (V
does not require the use of a reference voltage (V
termination voltage (V
LVCMOS2 — Low-Voltage CMOS for 2.5V
The Low-Voltage CMOS for 2.5V or lower (LVCMOS2) stan-
dard is an extension of the LVCMOS standard (JESD 8.5)
used for general purpose 2.5V applications. This standard
requires a 2.5V output source voltage (V
require the use of a reference voltage (V
mination voltage (V
LVTTL (2-24 mA)
LVCMOS2
PCI (3V/5V,
33 MHz/66 MHz)
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 Class I
and II
SSTL2 Class I
and II
CTT
AGP-2X
I/O Standard
Electronic
Industry
TT
Reference
).
TT
Voltage
(V
Input
).
0.75
1.25
1.32
N/A
N/A
N/A
0.8
1.0
0.9
0.9
1.5
1.5
REF
DS001-2 (v2.2) September 3, 2003
Alliance
)
Voltage
Source
Output
(V
N/A
N/A
3.3
2.5
3.3
1.5
1.5
1.5
3.3
2.5
3.3
3.3
CCO
Product Specification
Jedec
REF
CCO
)
) or a board ter-
), but does not
Termination
website
Voltage
Board
(V
0.75
1.25
N/A
N/A
N/A
N/A
CCO
REF
1.2
1.5
1.5
1.5
1.5
1.5
TT
)
) or a
), but
at
R