XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 2

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

DS001-1 (v2.4) September 3, 2003
Introduction
The Spartan™-II 2.5V Field-Programmable Gate Array fam-
ily gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in
mance is supported up to 200 MHz.
Spartan-II devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined Virtex-based architec-
ture. Features include block RAM (to 56K bits), distributed
RAM (to 75,264 bits), 16 selectable I/O standards, and four
DLLs. Fast, predictable interconnect means that successive
design iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
•
Table 1: Spartan-II FPGA Family Members
DS001-1 (v2.4) September 3, 2003
Product Specification
Notes:
1.
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
Second generation ASIC replacement technology
-
-
-
-
All user I/O counts do not include the four global clock/user input pins. See details in
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Densities as high as 5,292 logic cells with up to
200,000 system gates
Streamlined features based on Virtex architecture
Unlimited reprogrammability
Very low cost
development
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Logic
1,728
2,700
3,888
5,292
Cells
432
972
cycles,
(Logic and RAM)
R
System Gates
100,000
150,000
200,000
and
50,000
15,000
30,000
Table
inherent
1. System perfor-
risk
(R x C)
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
06
0
8 x 12
www.xilinx.com
Array
1-800-255-7778
CLB
of
0
Spartan-II 2.5V FPGA Family:
Introduction and Ordering
Information
Product Specification
•
•
•
CLBs
1,176
Total
216
384
600
864
96
System level features
-
-
-
-
-
-
-
-
-
-
-
Versatile I/O and packaging
-
-
-
-
-
Fully supported by powerful Xilinx development system
-
-
-
SelectRAM+™ hierarchical memory:
·
·
·
Fully PCI compliant
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
Low cost packages available in all densities
Family footprint compatibility in common packages
16 high-performance interface standards
Hot swap Compact PCI friendly
Zero hold time simplifies system timing
Foundation ISE Series: Fully integrated software
Alliance Series: For use with third-party tools
Fully automatic mapping, placement, and routing
User I/O
Maximum
Available
16 bits/LUT distributed RAM
Configurable 4K bit block RAM
Fast interfaces to external RAM
132
176
196
260
284
86
Table 3, page
(1)
Distributed RAM
13,824
24,576
38,400
55,296
75,264
3.
6,144
Total
Bits
Block RAM
Total
Bits
16K
24K
32K
40K
48K
56K
1