XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 64

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Clock Distribution Guidelines
Clock Distribution Switching Characteristics
T
Input
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in the way constitutes a worst-case limit.
1
DS001-3 (v2.7) September 3, 2003
Product Specification
Notes:
1.
Notes:
1.
GCLK Clock Skew
GCLK IOB and Buffer
Data Input Delay Adjustments
GPIO
T
T
These clock distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under
worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table
T
T
T
GPLVCMOS2
T
T
T
T
GSKEWIOB
T
Symbol
Symbol
Symbol
GPPCI33_3
GPPCI33_5
GPPCI66_3
Adjustments.
is specified for LVTTL levels. For other standards, adjust T
T
T
T
GPSSTL2
GPSSTL3
GPLVTTL
GPGTLP
T
GPHSTL
T
GPGTL
GPCTT
GPAGP
GPIO
GIO
R
Global clock skew between IOB flip-flops
Global clock pad to output
Global clock buffer I input to O output
Standard-specific global clock
input delay adjustments
Description
(1)
Description
Description
www.xilinx.com
1-800-255-7778
Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
PCI, 66 MHz, 3.3V
LVCMOS2
GPIO
Standard
SSTL2
SSTL3
LVTTL
GTL+
HSTL
AGP
GTL
CTT
with the values shown in
Delay Measurement Methodology, page
Max
0.13
Max
-6
0.7
0.7
-6
Speed Grade
–0.04
–0.11
–0.11
0.26
0.80
0.71
0.63
0.52
0.56
0.62
0.54
Speed Grade
-6
0
Speed Grade
I/O Standard Global Clock
Max
0.14
-5
Max
0.8
0.8
–0.05
–0.13
–0.13
-5
0.30
0.84
0.73
0.64
0.51
0.55
0.62
0.53
-5
0
Module 3 of 4
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10.
11