XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 34

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

The LOC properties use the following form:
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
Conflict Resolution
The block RAM memory is a true dual-read/write port RAM
that allows simultaneous access of the same memory cell
from both ports. When one port writes to a given memory
cell, the other port must not address that memory cell (for a
write or a read) within the clock-to-clock setup window. The
following lists specifics of port and memory cell write conflict
resolution.
•
•
Conflicts do not cause any physical damage.
Single Port Timing
Figure 32
RAM memory. The block RAM AC switching characteristics
are specified in the data sheet. The block RAM memory is
initially disabled.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus con-
tains the contents of the memory location, 0x00, as indi-
cated by the ADDR bus.
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors
the DI bus. The DI bus is written to the memory location
0x0F.
DS001-2 (v2.2) September 3, 2003
Product Specification
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
clock-to-clock setup requirement, the following occurs.
-
-
-
The write succeeds
The data out on the writing port accurately reflects
the data written.
The data out on the reading port is invalid.
shows a timing diagram for a single port of a block
R
LOC = RAMB4_R#C#
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1-800-255-7778
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
indicating that the block RAM memory is now disabled. The
DO bus retains the last value.
Dual Port Timing
Figure 33
read/write block RAM memory. The clock on port A has a
longer period than the clock on Port B. The timing parame-
ter T
The parameter, T
other timing parameters are identical to the single port ver-
sion shown in
T
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is vio-
lated for a WRITE-WRITE condition, the contents of the
memory at that location will be invalid. When the
clock-to-clock
WRITE-READ condition, the contents of the memory will be
correct, but the read port will have invalid data. At the first
rising edge of the CLKA, memory location 0x00 is to be writ-
ten with the value 0xAAAA and is mirrored on the DOA bus.
The last operation of Port B was a read to the same memory
location 0x00. The DOB bus of Port B does not change with
the new value on Port A, and retains the last read value. A
short time later, Port B executes another read to memory
location 0x00, and the DOB bus now reflects the new mem-
ory value written by Port A.
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the T
the DOB reflects the new memory values written by Port A.
BCCS
Spartan-II 2.5V FPGA Family: Functional Description
BCCS
is only of importance when the address of both ports
, (clock-to-clock setup) is shown on this diagram.
shows a timing diagram for a true dual-port
Figure
set-up
BCCS
32.
is violated once in the diagram. All
parameter
is
BCCS
violated
parameter and
Module 2 of 4
for
27
a