XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 32

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

5. A write operation requires only one clock edge.
6. A read operation requires only one clock edge.
The output ports are latched with a self timed circuit to guar-
antee a glitch free read. The state of the output port will not
change until the port executes another read or write opera-
tion.
Library Primitives
Figure 30
RAM primitives.
itives for synthesis and simulation.
DS001-2 (v2.2) September 3, 2003
Product Specification
Figure 31: Single-Port Block RAM Memory
Figure 30: Dual-Port Block RAM Memory
and
R
Figure 31
WEA
ENA
RSTA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
ADDRB[#:0]
DIB[#:0]
CLKA
Table 10
CLKB
WE
EN
RST
ADDR[#:0]
DI[#:0]
CLK
RAMB4_S#_S#
RAMB4_S#
show the two generic library block
describes all of the available prim-
DO[#:0]
DS001_32_061200
DOA[#:0]
DOB[#:0]
DS001_31_061200
www.xilinx.com
1-800-255-7778
Table 10: Available Library Primitives
RAMB4_S1
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
RAMB4_S2
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
RAMB4_S4
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
RAMB4_S16
RAMB4_S16_S16
Spartan-II 2.5V FPGA Family: Functional Description
Primitive
Port A Width
16
1
2
4
8
Port B Width
Module 2 of 4
N/A
N/A
N/A
N/A
N/A
16
16
16
16
16
1
2
4
8
2
4
8
4
8
8
25