XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 43

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
Output Slew Rate Property
As mentioned above, a variety of symbol names provide the
option of choosing the desired slew rate for the output buff-
ers. In the case of the LVTTL output buffers (OBUF, OBUFT,
and IOBUF), slew rate control can be alternatively pro-
gramed with the SLEW= property. By default, the slew rate
for each output buffer is reduced to minimize power bus
transients when switching non-critical signals. The SLEW=
property has one of the two following values.
Output Drive Strength Property
The desired output drive strength can be additionally speci-
fied by choosing the appropriate library symbol. The Xilinx
library also provides an alternative method for specifying
this feature. For the LVTTL output buffers (OBUF, OBUFT,
and IOBUF, the desired drive strength can be specified with
the DRIVE= property. This property could have one of the
following seven values.
Design Considerations
Reference Voltage (V
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (V
V
The voltage reference signal is "banked" within the device
on a half-edge basis such that for all packages there are
eight independent V
page 32
bank approximately one of every six I/O pins is automati-
cally configured as a V
Within each V
V
Module 2 of 4
36
REF
REF
SLEW=SLOW
SLEW=FAST
DRIVE=2
DRIVE=4
DRIVE=6
DRIVE=8
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
signal must be of the same type. Output buffers of any
as an external signal to the device.
for a representation of the I/O banks. Within each
REF
bank, any input buffers that require a
REF
REF
REF
banks internally. See
input.
) Pins
REF
). Provide the
Figure 35,
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1-800-255-7778
type and input buffers can be placed without requiring a ref-
erence voltage within the same V
Output Drive Source Voltage (V
Many of the low voltage I/O standards supported by Versa-
tile I/Os require a different output drive source voltage
(V
multiple output drive source voltages.
The V
packages. The VQ100 and the PQ208 provide one com-
bined V
provide four independent V
the FG456 provide eight independent V
Output buffers within a given V
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, PCI33_3, and PCI 66_3 use the V
for Input V
Transmission Line Effects
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short dis-
tance. Transmission line delays vary with inductance and
capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-
tent) termination or changes in the transmission line imped-
ance cause these reflections and can cause additional
delay in longer traces. As system speeds continue to
increase, the effect of I/O delays can become a limiting fac-
tor and therefore transmission line termination becomes
increasingly more important.
Termination Techniques
A variety of termination techniques reduce the impact of
transmission line effects.
The following lists output termination techniques:
Input termination techniques include the following:
CCO
None
Series
Parallel (Shunt)
Series and Parallel (Series-Shunt)
None
Parallel (Shunt)
). As a result each device can often have to support
CCO
CCO
CCO
supplies are internally tied together for some
supply. The TQ144 and the CS144 packages
voltage.
DS001-2 (v2.2) September 3, 2003
CCO
CCO
supplies. The FG256 and
REF
CCO
bank.
bank must share the
Product Specification
CCO
) Pins
supplies.
CCO
voltage
R