XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 27

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
Design Considerations
This section contains more detailed design information on
the following features:
•
•
•
Using Delay-Locked Loops
The Spartan-II FPGA family provides up to four fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits which improve and
simplify system level design.
Introduction
As FPGAs grow in size, quality on-chip clock distribution
becomes increasingly important. Clock skew and clock
delay impact device performance and the task of managing
clock skew and clock delay with conventional clock trees
becomes more difficult in large devices. The Spartan-II fam-
ily of devices resolve this potential problem by providing up
to four fully digital dedicated on-chip Delay-Locked Loop
(DLL) circuits which provide zero propagation delay and low
clock skew between output clock signals distributed
throughout the device.
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network min-
imizes clock skews due to loading differences. By monitor-
ing a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the indi-
vidual clock loads within the device.
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at
100 MHz. This technique can simplify board design
because the clock path on the board no longer distributes
such a high-speed signal. A multiplied clock also provides
designers the option of time-domain-multiplexing, using one
circuit twice per clock cycle, consuming less area than two
copies of the same circuit. Two DLLs in can be connected in
series to increase the effective clock multiplication factor to
four.
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.
Module 2 of 4
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Delay-Locked Loop . . . see
Block RAM . . . see
Versatile I/O . . . see
page 24
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page 20
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In order to guarantee the system clock establishes prior to
the device "waking up," the DLL can delay the completion of
the device configuration process until after the DLL
achieves lock.
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance clocks.
Library DLL Symbols
Figure 21
symbol, BUFGDLL. This macro delivers a quick and effi-
cient way to provide a system clock with zero propagation
delay throughout the device.
the two library DLL primitives. These symbols provide
access to the complete set of DLL features when imple-
menting more complex applications.
Figure 23: High-Frequency DLL Symbol CLKDLLHF
Figure 21: Simplified DLL Macro Symbol BUFGDLL
Figure 22: Standard DLL Symbol CLKDLL
shows the simplified Xilinx library DLL macro
I
CLKIN
CLKFB
CLKIN
CLKFB
RST
RST
0 ns
CLKDLLHF
CLKDLL
DS001-2 (v2.2) September 3, 2003
Figure 22
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLK0
CLK180
CLKDV
LOCKED
DS001_23_032300
Product Specification
O
DS001_22_032300
DS001_24_032300
and
Figure 23
show
R