XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 39

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
bank with an HSTL standard (V
not 5V tolerant.
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all pack-
ages there are eight independent V
See
each bank approximately one of every six I/O pins is auto-
matically configured as a V
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same stan-
dard. How to specify a specific location for the IBUF via the
LOC property is described below.
input standards compatibility requirements.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher per-
formance. To delay the input signal, activate the delay ele-
ment with the DELAY=TRUE property.
Table 15: Xilinx Input Standards Compatibility
Requirements
IBUFG
Signals used as high fanout clock inputs to the
Spartan-II device should drive a global clock input buffer
(IBUFG) via an external input port in order to take advan-
Module 2 of 4
32
Rule 1
Rule 2
Figure 35
All differential amplifier input signals within a
bank are required to be of the same standard.
There are no placement restrictions for inputs
with standards that require a single-ended input
buffer.
for a representation of the I/O banks. Within
Bank 0
Bank 5
Figure 35: I/O Banks
GCLK3
GCLK1
Spartan-II
Device
REF
GCLK2
GCLK0
CCO
input.
Table 15
< 2V), the input buffer is
Bank 1
Bank 4
REF
banks internally.
summarizes the
DS001_03_060100
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tage of one of the four dedicated global clock distribution
networks. The output of the IBUFG symbol can only drive a
CLKDLL, CLKDLLHF, or a BUFG symbol. The generic
IBUFG symbol appears in
The extension to the base name determines which I/O stan-
dard is used by the IBUFG. With no extension specified for
the generic IBUFG symbol, the assumed standard is
LVTTL.
The following list details variations of the IBUFG symbol.
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The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all pack-
ages there are eight independent V
See
each bank approximately one of every six I/O pins is auto-
matically configured as a V
IBUFG placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard. The
LOC property can specify a location for the IBUFG.
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol
represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
The Spartan-II BUFGP symbol can only be placed in a glo-
bal clock pad location. The LOC property can specify a
location for the BUFGP.
Figure 36: Global Clock Input Buffer (IBUFG) Symbol
IBUFG
IBUFG_LVCMOS2
IBUFG_PCI33_3
IBUFG_PCI33_5
IBUFG_PCI66_3
IBUFG_GTL
IBUFG_GTLP
IBUFG_HSTL_I
IBUFG_HSTL_III
IBUFG_HSTL_IV
IBUFG_SSTL3_I
IBUFG_SSTL3_II
IBUFG_SSTL2_I
IBUFG_SSTL2_II
IBUFG_CTT
IBUFG_AGP
Figure 35
for a representation of the I/O banks. Within
I
IBUFG
Figure
REF
DS001-2 (v2.2) September 3, 2003
DS001_37_061200
input.
36.
O
REF
Product Specification
banks internally.
R