XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 70

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Block RAM Switching Characteristics
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
DS001-3 (v2.7) September 3, 2003
Product Specification
Notes:
1.
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Clock CLK
Combinatorial Delays
Setup and Hold Times with Respect to TCK
Sequential Delays
T
T
T
T
T
T
TAPTCK /
BWCK
BACK
BDCK
BRCK
A zero hold time listing indicates no hold time or a negative hold time.
BECK
Symbol
T
T
T
T
T
Symbol
Symbol
BPWH
BPWL
TCKTDO
BCKO
BCCS
T
F
T
T
/ T
/ T
/ T
/ T
/ T
OFF
TCK
ON
IO
T
R
BCKD
BCKE
BCKR
BCKW
BCKA
TCKTAP
Clock CLK to DOUT output
ADDR inputs
DIN inputs
EN inputs
RST input
WEN input
Minimum pulse width, High
Minimum pulse width, Low
CLKA -> CLKB setup time for different ports
IN input to OUT output
TRI input to OUT output high impedance
TRI input to valid data on OUT output
TMS and TDI setup and hold times
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Description
Description
Description
(1)
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Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
1.4 / 0
1.4 / 0
2.9 / 0
2.7 / 0
2.6 / 0
Min
4.0 / 2.0
-
-
-
-
Min
-
-
-6
-6
Max
0.1
0.1
-6
0
Max
3.4
1.9
1.9
3.0
Speed Grade
Max
-
-
-
-
-
11.0
Speed Grade
Speed Grade
33
-
1.4 / 0
1.4 / 0
3.2 / 0
2.9 / 0
2.8 / 0
4.0 / 2.0
Min
Min
-
-
-
-
-
-
Max
0.2
0.2
-5
0
-5
-5
Max
Max
11.0
4.0
1.9
1.9
4.0
33
-
-
-
-
-
-
Module 3 of 4
Units
Units
ns
ns
ns
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17