XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 62

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

IOB Output Delay Adjustments for Different Standards
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
1
DS001-3 (v2.7) September 3, 2003
Product Specification
Notes:
1.
Output Delay Adjustments (Adj)
T
T
T
T
T
T
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables
T
T
T
T
T
T
T
T
T
T
T
T
T
OLVTTL_S12
OLVTTL_S16
OLVTTL_S24
T
T
T
T
T
OLVTTL_F12
OLVTTL_F16
OLVTTL_F24
T
OLVTTL_S2
OLVTTL_S4
OLVTTL_S6
OLVTTL_S8
OLVTTL_F2
OLVTTL_F4
OLVTTL_F6
OLVTTL_F8
OLVCMOS2
Symbol
OSSTL3_II
T
OHSTL_IV
OSSLT2_II
OPCI33_3
OPCI33_5
OPCI66_3
OHSTL_III
OSSTL2_I
OSSTL3_I
T
OHSTL_I
T
T
OGTLP
OAGP
OGTL
OCTT
Constants for Calculating T
R
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive
load, C
SL
)
Description
IOOP
and
Delay Measurement Methodology, page
www.xilinx.com
1-800-255-7778
Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
LVTTL, Slow, 2 mA
LVTTL, Fast, 2 mA
LVCMOS2
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
PCI, 66 MHz, 3.3V
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
AGP
Standard
(1)
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
10.
14.2
12.6
–0.1
–0.1
–0.3
–0.4
–0.8
–0.9
–0.4
–0.8
–0.4
–0.9
–0.5
–0.8
7.2
4.7
2.9
1.9
1.7
1.3
5.1
3.0
1.0
0.2
2.4
2.9
0.6
0.9
-6
0
Speed Grade
16.9
15.0
–0.1
–0.2
–0.4
–0.5
–1.0
–1.1
–0.5
–1.0
–0.5
–1.1
–0.6
–1.0
8.6
5.5
3.5
2.2
2.0
1.5
6.1
3.6
1.2
0.2
2.9
3.5
0.7
1.1
-5
0
Module 3 of 4
Units
ns
ns
ns
ns
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ns
ns
ns
ns
ns
ns
ns
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ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9