upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 110

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upd70f3017ay

Manufacturer Part Number
upd70f3017ay
Description
V850/sa1tm 32-/16-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet

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5.2.1 Operation
to the handler routine.
110
If a non-maskable interrupt request is generated, the CPU performs the following processing, and transfers control
<1> Saves the restored PC to FEPC.
<2> Saves the current PSW to FEPSW.
<3> Writes exception codes (0010H, 0020H) to the higher halfword (FECC) of ECR.
<4> Sets the NP and ID bits of the PSW and clears the EP bit.
<5> Loads the handler address (00000010H, 00000020H) of the non-maskable interrupt routine to the PC, and
transfers control.
INTC acknowledged
CPU processing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-1. Non-Maskable Interrupt Servicing
FEPC
FEPSW
ECR. FECC
PSW. NP
PSW. EP
PSW. ID
PC
Non-maskable interrupt request
Interrupt servicing
NMI input
PSW. NP
User’s Manual U12768EJ4V1UD
Restored PC
PSW
Exception code
1
0
1
Handler address
0
1
Handler address: 00000010H (NMI)
Interrupt request pending
00000020H (INTWDT)

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