upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 50

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(9) P90 to P96 (Port 9) ··· 3-state I/O
50
P90 to P96 constitute a 7-bit I/O port that can be set to input or output pins in 1-bit units.
P90 to P96 can also function as control signal output pins and bus hold control signal output pins when memory is
expanded externally.
During 8-bit access of port 9, the highest bit is ignored during a write operation and is read as a “0” during a read
operation.
The I/O signal level uses the bus interface power supply pins BV
(a) Port function
(b) Alternate functions (External expansion function)
P90 to P96 can be set to input or output in 1-bit units using the port 9 mode register (PM9).
P90 to P96 can be set to operate as control signal outputs for external memory expansion using the memory
expansion mode register (MM).
(i)
(ii) UBEN (Upper byte enable) ··· output
(iii) R/W (Read/write status) ··· output
(iv) DSTB (Data strobe) ··· output
LBEN (Lower byte enable) ··· output
This is a lower byte enable signal output pin for the external 16-bit data bus. During byte access of odd-
numbered addresses, these pins are set as inactive (high level). The output changes in synchronization
with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as
inactive, the previous bus cycle’s address is retained.
This is an upper byte enable signal output pin for the external 16-bit data bus. During byte access of
even-numbered addresses, these pins are set as inactive (high level).
synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets
the bus cycle as inactive, the previous bus cycle’s address is retained.
This is an output pin for the status signal pin that indicates whether the bus cycle is a read cycle or write
cycle during external access. High level is set during a read cycle and low level is set during a write
cycle. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus
cycle. High level is set when the timing sets the bus cycle as inactive.
This is an output pin for the external data bus’s access strobe signal. Output becomes active (low level)
during the T2 and TW states of the bus cycle. Output becomes inactive (high level) when the timing
sets the bus cycle as inactive.
Word access
Halfword access
Byte access
Access
Even-numbered address
Odd-numbered address
CHAPTER 2 PIN FUNCTIONS
User’s Manual U12768EJ4V1UD
UBEN
0
0
1
0
DD
and BV
LBEN
0
0
0
1
SS
as a reference.
A0
0
0
0
1
The output changes in