upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 235

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Condition for clearing (WREL = 0)
• Automatically cleared after execution
• When RESET is input
Condition for clearing (SPIE = 0)
• Cleared by instruction
• When RESET is input
This bit’s setting is invalid during an address transfer and is valid as the transfer is completed. When in master mode,
a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a
local address, a wait is inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave
device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM = 0)
• Cleared by instruction
• When RESET is input
Condition for clearing (ACKE = 0)
• Cleared by instruction
• When RESET is input
WREL
WTIM
ACKE
SPIE
Note
0
1
0
1
0
1
0
1
This flag’s signal is invalid when IICE = 0.
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode:
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode:
Wait not canceled
Wait canceled. This setting is automatically cleared after wait is canceled.
Disabled
Enabled
Acknowledgement disabled.
Acknowledge enabled. During the ninth clock period, the SDA line is set to low level. However, the ACK
is invalid during address transfers and is valid when EXC = 1.
Enable/Disable Generation of Interrupt Request when Stop Condition is Detected
After input of nine clocks, the clock is set to low level and wait is set for the master device.
After input of eight clocks, the clock is set to low level and wait is set for the master device.
Note
CHAPTER 10
Note
Note
Note
Control of Wait and Interrupt Request Generation
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION
Wait Cancellation Control
Acknowledge Control
Condition for setting (WREL = 1)
• Set by instruction
Condition for setting (SPIE = 1)
• Set by instruction
Condition for setting (WTIM = 1)
• Set by instruction
Condition for setting (ACKE = 1)
• Set by instruction
(2/4)
235