upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 331

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

12.3
(1) DMA transfer request control block
(2) Channel control block
The DMA transfer request control block generates a DMA transfer request signal for the CPU when the DMA
transfer trigger (INT signal) specified by DMA channel control register n (DCHCn) is input.
When the DMA transfer request signal is acknowledged, the CPU generates a DMA transfer acknowledge signal
for the channel control block and interface control block after the current CPU processing has finished.
The channel control block distinguishes the DMA transfer channel n (DMA0 to DMA2) to be transferred and
controls the internal RAM, peripheral I/O addresses, and access cycles (internal RAM: 1 clock, peripheral I/O
register: 3 clocks) set by the peripheral I/O registers of the channel to be transferred, the transfer direction, and
the transfer count. In addition, it also controls the priority order when two or more DMAn transfer triggers (INT
signals) are generated simultaneously.
Remark n = 0 to 2
Configuration
DMA peripheral I/O address
DMA internal RAM address
register n (DIOAn)
register n (DBCn)
register n (DRAn)
DMA byte count
DMA transfer trigger
(INT signal)
INTDMAn
Figure 12-1. Block Diagram of DMAC
CHAPTER 12 DMA FUNCTIONS
Channel controller
User’s Manual U12768EJ4V1UD
request control
DMA transfer
I/O register
Peripheral
Interface control
DMA channel control
register n (DCHCn)
Internal bus
DMA transfer acknowledge signal
Internal
RAM
CPU
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