upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 249

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(6) Wait signal (WAIT)
The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to
transmit or receive data (i.e., is in a wait state).
Setting the SCL pin to low level notifies the communication partner of the wait status. When the wait status has
been canceled for both the master and slave devices, the next data transfer can begin.
Transfer lines
(a) When master device has a nine-clock wait and slave device has an eight-clock wait
Master
Slave
ACKE
SDA
SCL
SCL
SCL
IIC0
IIC0
(master: transmission, slave: reception, and ACKE = 1)
H
CHAPTER 10
D2
6
6
Figure 10-14. Wait Signal (1/2)
D1
7
7
Master returns to high
impedance but slave
is in wait state (low level)
Wait after output
of eighth clock
User’s Manual U12768EJ4V1UD
D0
8
8
SERIAL INTERFACE FUNCTION
9
ACK
9
FFH is written to IIC0 or WREL is set to 1
Wait after output
of ninth clock
IIC0 data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
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