upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 144

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(3) Software STOP mode
(4) Subclock operation
6.4.2 HALT mode
(1) Settings and operating states
(2) Release of HALT mode
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This mode stops the entire system by stopping the main clock oscillator. The subclock continues to be supplied
to keep on-chip peripheral functions operating. If a subclock is not used, ultra low power consumption mode
(current that flows through the on-chip feedback resistor of the subclock oscillator and leakage current only are
flowing) is set. Software STOP mode setting is prohibited if the CPU is operating via the subclock.
If the STP bit of the PSC register is set to 1, the system enters software STOP mode.
In this mode, the CPU clock is set to operate using the subclock and the MCK bit of the PCC register is set to 1 to
set low power consumption mode in which the entire system operates using only the subclock.
When HALT mode is set, the CPU’s operating clock is stopped so that power consumption can be reduced.
When IDLE mode is set, the CPU’s operating clock and some peripheral functions (DMAC and BCU) are stopped,
so that power consumption can be reduced even more than in HALT mode.
In this mode, the clock’s oscillator continues to operate but the CPU’s operating clock is stopped. A clock
continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. When
HALT mode is set while the CPU is idle, it enables the system’s total power consumption to be reduced.
In HALT mode, execution of programs is stopped but the contents of all registers and internal RAM are retained
as they were just before HALT mode was set. In addition, all on-chip peripheral functions that do not depend on
instruction processing by the CPU continue operating.
HALT mode can be set by executing the HALT instruction. It can be set when the CPU is operating via either the
main clock or subclock.
The operating statuses in the HALT mode are listed in Table 6-1.
HALT mode can be released by an NMI request, an unmasked maskable interrupt request, or RESET input.
(a) Release by interrupt request
(b) Release by RESET pin input
HALT mode is released regardless of the priority level when an NMI request or an unmasked maskable
interrupt request occurs. However, the following occurs if HALT mode was set as part of an interrupt
servicing routine.
(i)
(ii) When an interrupt request (including NMI request) that has a higher priority level than the interrupt
This is the same as for normal reset operations.
Only HALT mode is released when an interrupt request that has a lower priority level than the interrupt
currently being serviced occurs, and the lower-priority interrupt request is not acknowledged. The
interrupt request itself is retained.
currently being serviced occurs, HALT mode is released and the interrupt request is acknowledged.
CHAPTER 6 CLOCK GENERATION FUNCTION
User’s Manual U12768EJ4V1UD