upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 236

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

236
Cautions concerning set timing
• For master reception:
• For master transmission: Note that a start condition cannot be generated normally during the ACK period.
• Cannot be set at the same time as SPTn
Condition for clearing (STT = 0)
• Cleared by instruction
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• Cleared by LREL = 1
• When IICE = 0
• Cleared when RESET is input
Remark
device
STT
0
1
Start conditions not generated.
When bus is released (in STOP mode):
When bus is not used:
In the wait state (when master device):
Bit 1 (STT) is 0 if it is read immediately after data setting.
Generate a start condition (for starting as master). The SDA line is changed from high level to low
level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCL
is changed to low level.
This trigger functions as a start condition reserve flag. When set, it releases the bus and then
automatically generates a start condition.
Generate a restart condition after releasing the wait.
Cannot be set during transfer. Can be set only when ACKE has been set to 0 and slave
has been notified of final reception.
CHAPTER 10
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION
Start Condition Trigger
Condition for setting (STT = 1)
• Set by instruction
(3/4)