upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 338

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

12.5 Operation
DCHC2)) is generated during CPU processing, a single DMA transfer is started after the current CPU processing has
finished. Regardless of the transfer direction, 4 CPU clocks (f
clocks are divided as follows.
the next DMA transfer request (INTxxx). After the specified number of data transfers ends, the DMA transfer end
interrupt requests (INTDMA0 to INTDMA2) are generated for each channel of the interrupt controller if the TCn bit of
the DOCHn register becomes 1.
priority order of DMA0 > DMA1 > DMA2. While a higher priority DMA transfer request is being executed, the lower
priority DMA transfer requests are held pending. After the higher priority DMA transfer ends, control always shifts to
the CPU processing once, and then the lower priority DMA transfer request is executed after the CPU processing
ends.
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The DMA controller of the V850/SA1 supports only the single transfer mode.
When a DMA transfer request (INTxxx: refer to 12.4 (4) DMA channel control registers 0 to 2 (DCHC0 to
• Internal RAM access: 1 clock
• Peripheral I/O access: 3 clocks
After one DMA transfer (8/16 bits) ends, control always shifts to the CPU processing and waits for the generation of
The DMA transfer operation timing chart is shown below.
Access destination for transfer from
If two or more DMA transfer requests are generated simultaneously, the DMA transfer requests are executed in a
The processing when the transfer requests DMA0 to DMA2 are generated simultaneously is shown below.
internal RAM to peripheral I/O
DMA transfer request signal
Remark n = 0 to 2
Processing format
t
CPU
CPU processing
Figure 12-4. DMA Transfer Operation Timing
CHAPTER 12 DMA FUNCTIONS
User’s Manual U12768EJ4V1UD
RAM
Peripheral I/O
DMA transfer
processing
4 clocks
Peripheral I/O
INTMDAn occurs when the
number of transfers specified
by the DBCn register end
CPU
RAM
) are required for one DMA transfer. The 4 CPU
CPU processing
RAM
Peripheral I/O RAM
DMA transfer
processing
4 clocks
Peripheral I/O
INTMDAn occurs when the
number of transfers specified
by the DBCn register end
CPU processing