upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 270

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

10.3.7 Address match detection method
address.
local address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave
address sent by the master device, or when an extension code has been received.
10.3.8 Error detection
(IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data
to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
10.3.9 Extension code
270
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code reception flag (EXC)
(2) If 11110xx0 is set to SVA0 by a 10-bit address transfer and 11110xx0 is transferred from the master device, the
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
In I
Address match detection is performed automatically by hardware. An interrupt request (INTIIC0) occurs when a
In I
Note EXC:
is set for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth
clock.
The local address stored in slave address register 0 (SVA0) is not affected.
results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC = 1
• Seven bits of data match: COI = 1
code, such processing is performed by software.
For example, when operation as a slave is not desired after the extension code is received, set bit 6 of IIC control
register 0 (IICC0) to LREL = 1 and the CPU will enter the next communication wait state.
2
2
C bus mode, the status of the serial data bus (SDA) during data transmission is captured by IIC shift register 0
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
COI:
Slave Address
Bit 5 of IIC status register 0 (IICS0)
Bit 4 of IIC status register 0 (IICS0)
0000
0000
0000
0000
1111
000
000
001
010
0xx
CHAPTER 10
Table 10-4. Extension Code Bit Definitions
R/W Bit
Note
X
X
X
0
1
User’s Manual U12768EJ4V1UD
Note
General call address
Start byte
CBUS address
Address that is reserved for a different bus format
10-bit slave address specification
SERIAL INTERFACE FUNCTION
Description