upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 272

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK signal transfer period after data reception
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to output a
restart condition
When stop condition is detected while attempting to output
a restart condition
When data is at low level while attempting to output a stop
condition
When SCL is at low level while attempting to output a
restart condition
10.3.11 Wakeup function
extension code have been received. This function makes processing more efficient by preventing unnecessary
interrupt requests from occurring when addresses do not match.
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
output a start condition) to a slave device.
wakeup function, and this determines whether interrupt requests are enabled or disabled.
272
Notes 1.
Remark
The I
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
However, when a stop condition is detected, bit 5 (SPIE) of IIC control register 0 (IICC0) is set regardless of the
2
C bus slave function is a function that generates an interrupt request (INTIIC0) when a local address and
2.
SPIE: Bit 5 of IIC control register 0 (IICC0)
When WTIM (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge of
the ninth clock. When WTIM = 0 and the extension code’s slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
When there is a possibility that arbitration will occur, set SPIE = 1 for master device operation.
Status During Arbitration
Table 10-5. Status During Arbitration and Interrupt Request Generation Timing
CHAPTER 10
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION
At falling edge of eighth or ninth clock following byte transfer
When stop condition is output (when SPIE = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is output (when SPIE = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
Note 2
Note 2
Note 1
Note 1
Note 1