upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 215

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upd70f3017ay

Manufacturer Part Number
upd70f3017ay
Description
V850/sa1tm 32-/16-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet

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9.2 Configuration
Control registers
9.3 Watchdog Timer Control Register
(1) Oscillation stabilization time select register (OSTS)
The watchdog timer consists of the following hardware.
Three registers control the watchdog timer.
• Oscillation stabilization time select register (OSTS)
• Watchdog timer clock select register (WDCS)
• Watchdog timer mode register (WDTM)
This register selects the oscillation stabilization time after a reset is applied or the software STOP mode is
released until the oscillation is stable.
OSTS is set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H.
OSTS
After reset: 04H
Item
OSTS2
Other than above
0
0
0
0
1
7
0
OSTS1
R/W
0
0
1
1
0
6
0
Table 9-3. Watchdog Timer Configuration
OSTS0
Oscillation stabilization time select register (OSTS)
Watchdog timer clock select register (WDCS)
Watchdog timer mode register (WDTM)
0
1
0
1
0
CHAPTER 9
User’s Manual U12768EJ4V1UD
5
0
2
2
2
2
2
(after reset)
Setting prohibited
Address: FFFFF380H
14
16
17
18
19
/f
/f
/f
/f
/f
XX
XX
XX
XX
XX
Clock
WATCHDOG TIMER
4
0
Oscillation Stabilization Time Selection
819
3.3 ms
6.6 ms
13.1 ms
26.2 ms
20 MHz
µ
s
3
0
Configuration
964
3.855 ms
7.710 ms
15.42 ms
30.84 ms
17 MHz
OSTS2
µ
2
s
f
XX
1.6 ms
6.6 ms
13.1 ms
26.2 ms
52.4 ms
10 MHz
OSTS1
1
8.2 ms
32.8 ms
65.5 ms
131.1 ms
262.1 ms
OSTS0
2 MHz
0
215

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