upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 305

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(iv) Reception
The receive operation is enabled when “1” is set to bit 6 (RXEn) of asynchronous serial interface mode
register n (ASIMn), and the input via the RXDn pin is sampled.
The serial clock specified by baud rate generator control register n (BRGCn) is used when sampling the
RXDn pin.
When the RXDn pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling
is output when half of the specified baud rate time has elapsed. If sampling the RXDn pin input with this start
timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and
starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit, and
one-bit stop bit are detected, at which point reception of one data frame is completed.
Once reception of one data frame is completed, the receive data in the shift register is transferred to receive
buffer register n (RXBn) and a receive completion interrupt (INTSRn) occurs.
Even if an error has occurred, the receive data in which the error occurred is still transferred to RXBn.
When an error occurs, INSTRn is generated if bit 1 (ISRMn) of ASIMn is cleared (0). On the other hand,
INTSRn is not generated if the ISRMn bit is set (1) (see 10.4.2 (1) Asynchronous serial interface mode
registers 0 and 1 (ASIM0, ASIM1).
If the RXEn bit is reset to 0 during a receive operation, the receive operation is stopped immediately. At this
time, the contents of RXBn and ASISn do not change, nor does INTSRn or INTSERn occur.
The timing of the asynchronous serial interface receive completion interrupt is shown below.
RXDn (input)
Caution Be sure to read the contents of receive buffer register n (RXBn) even when a receive
Remarks 1. n = 0, 1
Figure 10-33. Timing of Asynchronous Serial Interface Receive Completion Interrupt
INTSRn
error has occurred. If the contents of RXBn are not read, an overrun error will occur
during the next data receive operation and the receive error status will remain.
2.
The interrupt control register of INTSR0 is alternately used as the interrupt control register
(CSIC1) of INTCSI1. An SRIC0 register does not exist.
START
CHAPTER 10
D0
User’s Manual U12768EJ4V1UD
D1
SERIAL INTERFACE FUNCTION
D2
D6
D7
Parity
STOP
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