upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 336

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(4) DMA channel control registers 0 to 2 (DCHC0 to DCHC2)
336
(n = 0 to 2)
After reset:
DCHCn
These registers are used to control the DMA transfer operation mode for DMA channel n.
These registers are can be read/written in 1-bit or 8-bit units.
Notes 1. TCn (n = 0 to 2) is set to 1 when a specified number of transfers are completed, and is
Cautions 1. DMA transfer is started using an interrupt request signal (INTxxn above)
00H
Channel n
DADn
TCn
TCn
0
1
0
1
7
0
1
2
2. INTIIC0 is available only in the
cleared to 0 when a write instruction is executed.
703017AY, 70F3015BY, and 70F3017AY.
2. If the INTxxn signal is generated in synchronization with the external clock, do
R/W
The trigger of the DMA transfer generated in synchronization with the external
generated from an on-chip peripheral I/O. DMA transfer is not started even if
the xxIFn bit of the interrupt control register (xxICn) that is the target of the
INTxxn signal is set 1.
not set the INTxxn signal as multiple DMA transfer triggers at the same time.
For example, do not set INTCSI0 as the trigger of both DMA channel 0 and DMA
channel 1.
clock is shown below.
• INTCSI0 when SCK0 pin input is selected as serial clock
• INTCSI0 when timer 2 output (TO2) that operates with TI2 pin input is selected
• INTTM4 when TI4 pin input is selected as count clock.
Not completed
Completed
Increment
Address is fixed
TTYPn1
as serial clock
0
0
1
1
0
0
1
1
0
0
1
1
6
0
Address:
TTYPn0
CHAPTER 12 DMA FUNCTIONS
DADn
0
1
0
1
0
1
0
1
0
1
0
1
User’s Manual U12768EJ4V1UD
5
Internal RAM Address Count Direction Control
DMA Transfer Completed/Not Completed
DCHC0: FFFFF186H, DCHC1: FFFFF196H, DCHC2: FFFFF1A6H
INTCSI0/INTIIC0
INTTM00
INTAD
INTTM4
INTCSI1/INTSR0
INTST1
INTPCSI0/INTIIC0
INTTM4
INTSR1
INTST0
INTAD
INTTM5
TTYPn1
4
µ
PD703014Y, 703014BY, 703015AY, 703015BY,
TTYPn0
Setting of Trigger for DMA Transfer
Note 2
Note 2
3
TDIRn
2
Note 1
DSn
1
ENn
0
(1/2)